{"id":3622386,"url":"https://alion.io/job/nanocorechip-aixinkatajiagoushi","title":"AI芯片架构师","company":{"id":4407431,"name":"Nanocorechip","domain":"nanocorechip.com","url":"https://alion.io/company/nanocorechip","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hangzhou, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":30000,"max":60000,"currency":"CNY","period":"month","gross":null,"usd_annual":108576},"salary_estimate":null,"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"DLP","optional":false},{"name":"LLM","optional":false},{"name":"MLIR","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-11-02T09:56:49Z","employer_posted_date":null,"last_verified_at":"2026-11-02T09:56:49Z","board_verified":false,"closed_at":null,"days_open":9,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":9},"description":"1.AI大模型推理芯片-芯片（WholeChip）总架构设计工程师\n\n岗位定位 作为芯片系统架构的“总设计师”，主导面向大语言模型（LLM）推理的高吞吐、低延迟AI芯片的顶层架构定义，拉通核心计算、互连与存储子系统，确保整体PPA（性能、功耗、面积）在先进制程下达到行业顶尖水平。\n\n核心岗位职责\n\n· 负责大模型推理芯片的WholeChip系统架构定义、软硬件划分及规格制定（PRD/EAS）。\n\n· 深入分析Transformer类模型（如GPT,LLaMA）的推理特征，突破Prefill与Decode阶段的算力及访存带宽瓶颈，定义最优的全局数据流（Dataflow）。\n\n· 协同多核计算、NoC、存储及接口（如HBM、PCIe/CXL）团队，制定全芯片的互连拓扑与资源分配策略。\n\n· 搭建系统级分析模型，主导架构级的性能评估（PerformanceProjection）与瓶颈分析（BottleneckAnalysis）。\n\n· 深度参与流片及Bring-up阶段，协同底层软件栈与驱动团队完成系统级性能调优与软硬件协同设计（Hardware-SoftwareCo-design）。\n\n· 追踪业界前沿AI算法演进趋势及竞品架构，主导下一代芯片架构的预研与演进规划。\n\n任职资格要求\n\n· 基础硬性要求：微电子、计算机、集成电路等相关专业硕士及以上学历；社招需5年以上（高级/资深）芯片架构设计经验，校招需具备相关领域深度的博士研究背景。\n\n· 必备专业技能：\n\n1. 精通计算机体系结构，具备至少一款大规模复杂SoC或AI大算力芯片的WholeChip架构定义及成功流片经验。\n\n2. 深刻理解AI大模型推理的底层逻辑，熟悉GEMM算力边界、MemoryBound问题及KVCache的显存调度机制。\n\n3. 熟悉2nm/3nm/5nm等先进制程的物理实现约束，在架构定义初期能有效评估功耗与面积（PPA）边界。\n\n4. 熟练掌握C/C++及Python，具备优秀的架构建模分析能力及硬件直觉。\n\n加分项\n\n· 具备国际头部AI芯片公司（如Nvidia,AMD,GoogleTPU团队等）核心架构设计经验者优先。\n\n· 深入理解算子融合（OperatorFusion）、稀疏化（Sparsity）及低精度量化（FP8/INT4）等大模型推理加速技术。\n\n· 熟悉编译框架（如TVM,MLIR）及软硬协同优化机制。\n\n2.AI大模型推理芯片-多核AI计算核架构设计工程师\n\n岗位定位 聚焦AI大模型推理的“算力引擎”，主导高性能、高能效多核AI计算核（NPUCore/TensorCore）的微架构设计，实现大模型张量运算与标量/向量运算的极致加速。\n\n核心岗位职责\n\n· 定义AI计算核（NPU/MatrixEngine）的指令集架构（ISA）与微架构，满足大模型复杂算子的高效执行需求。\n\n· 设计并优化面向大模型推理的高并发、深流水线架构，针对矩阵乘法（GEMM）设计高吞吐的张量计算单元（TensorUnit）。\n\n· 针对大模型中的非线性函数（如Softmax,SwiGLU,LayerNorm）及特殊算子，设计高效的向量处理单元（VectorUnit）。\n\n· 主导低精度数字信号处理架构定义，深度优化FP8、BF16及INT8/INT4数据格式的混合精度计算效率及硬件开销。\n\n· 解决多核并行计算下的任务调度与同步开销问题，提升多核系统的整体算力利用率（Utilization）。\n\n· 协同验证与物理设计团队，解决先进制程下高频计算核的TimingClosure及动态功耗挑战。\n\n任职资格要求\n\n· 基础硬性要求：微电子、电子工程、计算机等相关专业硕士及以上学历；社招需5年以上处理器核或AI加速器微架构设计经验。\n\n· 必备专业技能：\n\n1. 精通处理器体系结构，深入理解指令级并行（ILP）、数据级并行（DLP）及多线程技术。\n\n2. 熟练掌握Verilog/SystemVerilog，具备扎实的RTL编码与微架构设计能力。\n\n3. 深刻理解大模型中矩阵运算（MatMul）的底层硬件映射原理，熟悉SystolicArray等经典AI计算架构。\n\n4. 熟悉计算机算术逻辑（ComputerArithmetic），具备浮点数/定点数运算器的高效设计经验。\n\n加分项\n\n· 具备RISC-V架构深度定制及扩展指令集（CustomISA）设计经验者优先。\n\n· 有过成功的高性能DSP、GPUShader或NPUCore流片经验。\n\n· 熟悉微架构级别的低功耗设计（ClockGating,PowerGating,DVFS）。\n\n3.AI大模型推理芯片-NoC互连拓扑与架构设计工程师\n\n岗位定位 打造全芯片的高速“交通网络”，主导设计高带宽、低延迟、无拥塞的片上网络（NoC），突破大模型海量数据在多核与存储器之间的搬移瓶颈。\n\n核心岗位职责\n\n· 针对AI大模型推理过程中的广播（Broadcast）、组播（Multicast）及All-Reduce等复杂通信模式，定义最优的片上网络拓扑结构（如Mesh,Ring,Torus等）。\n\n· 设计高性能NoC路由器（Router）微架构，优化虚通道（VirtualChannel）分配、缓冲队列（Buffer）与路由算法，将片上通信延迟降至最低。\n\n· 结合后端物理实现（Floorplan），解决SRAM与Crossbar等模块在先进制程下的高密度布局挑战，通过架构级预判缓解布线拥塞（RoutingCongestion）。\n\n· 定义并实现多级服务质量（QoS）策略，确保大模型推理中关键路径数据的最高优先级与绝对带宽保障。\n\n· 负责片上网络死锁（Deadlock）避免方案的设计与形式化验证规划。\n\n· 协同存储架构团队，优化计算核到分布式SRAM及HBM的高效访问路径。\n\n任职资格要求\n\n· 基础硬性要求：计算机、集成电路等相关专业硕士及以上学历；社招需3年以上高性能NoC或互连网络架构设计经验。\n\n· 必备专业技能：\n\n1. 深入理解片上网络（Network-on-Chip）拓扑学、路由算法及流控（FlowControl）机制。\n\n2. 精通AMBAAXI/CHI等主流片上互连协议，熟悉缓存一致性（CacheCoherence）原理。\n\n3. 具备极强的物理感知能力（Physical-AwareDesign），能够评估互连架构在先进制程Floorplan下的Timing与WireRouting可行性。\n\n4. 熟练使用C++/Python进行互连网络的周期级抽象建模与Traffic仿真验证。\n\n加分项\n\n· 曾主导或深度参与过32核以上规模SoC的NoC架构设计及流片。\n\n· 熟悉大模型分布式训练与推理的集合通信库（如NCCL）及底层硬件映射。\n\n具备基于商业化NoCIP（如Arteris,Sonics,ARMCoreLink）的二次深度开发与优化经验。\n\n4.AI大模型推理芯片-多芯片集成（Chiplet）架构设计工程师\n\n岗位定位 打破单一芯片物理面积的算力天花板，主导多Die互连的Chiplet系统架构定义，实现大模型推理所需超大参数量的Scale-Out横向扩展。\n\n核心岗位职责\n\n· 主导多芯片互连（Die-to-Die）的系统级架构设计，定义合理的逻辑拆分（Partition）与Chiplet拓扑方案。\n\n· 负责Die-to-Die(D2D)高速互连协议栈（Protocol/Link/MAC层）的定义与选型，优化多Die间的数据包封装以降低传输延迟。\n\n· 针对大语言模型跨Die的KVCache同步与激活函数传递，设计高带宽、低延迟的硬件级数据一致性或高效通信机制。\n\n· 协同先进封装（AdvancedPackaging）团队，评估CoWoS、InFO等2.5D/3D封装技术下的布线密度与热功耗约束，反推架构设计的可行性。\n\n· 解决多Die系统的全局时钟同步（Synchronization）、复位、测试（DFT）及电源输配电网络（PDN）的架构级挑战。\n\n任职资格要求\n\n· 基础硬性要求：微电子、集成电路等相关专业硕士及以上学历；社招需3年以上先进互连或Chiplet架构设计经验。\n\n· 必备专业技能：\n\n1. 深入理解UCIe、BoW等行业主流Die-to-Die互连标准与底层物理层（PHY）工作原理。\n\n2. 具备跨物理边界的系统级架构思维，能够量化评估延迟隐藏（LatencyHiding）策略。\n\n3. 了解TSMC2.5D/3D等先进封装技术的基础特性及对架构设计的约束边界。\n\n4. 熟悉高速SerDes或并行接口架构设计与系统级集成。\n\n加分项\n\n· 有过基于CoWoS或类似先进封装技术的成功流片及量产经验。\n\n· 在系统级高速接口（如NVLink,CXL）协议层设计领域有深度积累。\n\n· 具备信号完整性（SI）与电源完整性（PI）的架构级前瞻评估能力。\n\n5.AI大模型推理芯片-存储子系统架构设计工程师\n\n岗位定位 攻克大模型推理最核心的显存墙瓶颈，主导构建由片上SRAM与片外HBM/LPDDR构成的超大容量、极高带宽的立体存储体系。\n\n核心岗位职责\n\n· 定义面向大语言模型推理的Multi-Level存储层级架构（如L1/L2分布式SRAM至片外HBM3/HBM4）。\n\n· 深入分析LLM长文本推理场景下KVCache的容量与带宽需求，设计定制化的片上缓存（Cache）与便签存储器（ScratchpadMemory）管理机制。\n\n· 负责存储控制器（MemoryController）的前端架构优化，设计高效的数据重排（Reordering）、突发传输（Burst）及带宽利用率提升算法。\n\n· 解决多核高并发访问下的SRAMBank冲突问题，结合Floorplan约束定义最优的物理SRAM切分与聚合方案。\n\n· 与编译器及底层软件团队紧密合作，提供易于软件切分（Tiling）及显存分配（MemoryAllocation）的底层硬件接口。\n\n任职资格要求\n\n· 基础硬性要求：微电子、计算机等专业硕士及以上学历；社招需5年以上复杂SoC存储子系统架构或RTL设计经验。\n\n· 必备专业技能：\n\n1. 极度精通HBM2e/HBM3/HBM4或LPDDR5/DDR5的底层协议规范及存储控制器微架构。\n\n2. 深入理解Cache管理策略、一致性协议以及片上SRAM的高速读写机制。\n\n3. 具备针对MemoryBound场景下系统级访存瓶颈的精确分析与调优能力。\n\n4. 熟悉先进制程下SRAMCompiler的特性及PPA权衡边界。","description_format":"text","description_chars":4411,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":[],"lifecycle":[{"event":"open","at":"2026-11-02T18:37:15Z"}],"visa":[],"liveness":{"score":89,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.893,"p_room":1,"age_days":8,"expected_fill_days":30,"reasons":["seen:8","velocity","win:early"],"computed_at":"2026-11-11T05:49:22Z"},"pay":{"stated_usd_annual":108576,"is_top_pay":false},"html_url":"https://alion.io/job/nanocorechip-aixinkatajiagoushi","json_url":"https://alion.io/job/nanocorechip-aixinkatajiagoushi.json","meta":{"generated_at":"2026-11-12T09:34:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19464,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4407431},"rest":"https://alion.io/mcp/rest/get_company?id=4407431"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnanocorechip-aixinkatajiagoushi"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnanocorechip-aixinkatajiagoushi"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnanocorechip-aixinkatajiagoushi"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nanocorechip-aixinkatajiagoushi\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnanocorechip-aixinkatajiagoushi"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3622386}},{"tool":"search_jobs","arguments":{"company":"nanocorechip.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3622386},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}