{"id":4203474,"url":"https://alion.io/job/netlist-ai-hardware-memory-systems-architect","title":"AI Hardware / Memory Systems Architect","company":{"id":691714,"name":"Netlist","domain":"netlist.com","url":"https://alion.io/company/netlist","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Breezy","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":285000,"max":null,"currency":"USD","period":"year","gross":null,"usd_annual":285000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Edge AI","optional":false},{"name":"KV Cache","optional":false},{"name":"LLM","optional":false},{"name":"RAG","optional":false},{"name":"CUDA","optional":true},{"name":"Transformers","optional":true},{"name":"vLLM","optional":true}],"status":"live","first_seen_at":"2026-11-12T16:12:45Z","employer_posted_date":"2026-11-12","last_verified_at":"2026-11-12T23:00:47Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"AI Hardware / Memory Systems Architect\nReports To: VP, Engineering\nCompany Overview:\nNetlist, Inc. (OTCQB: NLST) is a leading provider of high-performance modular memory subsystems and next-generation storage-class memory solutions. We specialize in cutting-edge technologies that enable innovation in AI, cloud computing, and enterprise infrastructure. Our product portfolio includes DDR4/DDR5 DIMMs, NAND-based SSDs, and advanced interconnect technologies such as CXL and PCIe.\nJoin our world-class engineering team and be part of shaping the future of memory and storage architecture.\nPosition Summary:\nThis is a senior technical architecture role for an individual who understands how AI workloads translate into memory, bandwidth, latency, compute, interconnect, power, and system-level requirements.\nThe successful candidate will work closely with the Chief AI Systems Architect, AI Product Strategist, AI Inference / Systems Software Architect, and R&D engineering teams to translate customer problems and AI workload requirements into innovative hardware and memory architectures.\nWe are particularly interested in investigating opportunities involving:\nEvolution of memory hierarchy as AI models and context sizes grow\nType of data that will reside in HBM, DDR, CXL memory, storage\nMoving computation closer to memory\nReduce energy and cost of moving data\nIncrease effective memory capacity without proportionally increasing system cost and power\nNew memory or hardware architecture that can provide a meaningful advantage over today's solutions\nThe role is for someone who can design the memory and hardware architecture to solve the problem with the best performance, power, capacity, and cost.\nKey Responsibilities:\nAI Hardware and Memory Architecture\nDevelop system and hardware architectures for next-generation AI and inference platforms\nAnalyze AI workloads and translate workload characteristics into memory hierarchy, bandwidth, latency, capacity, and compute requirements\nArchitect solutions spanning HBM, DDR, CXL memory, memory pooling and disaggregation, memory controllers, cache hierarchy, AI accelerators, near-memory computing, processing-in-memory and storage and persistent memory\nDevelop architectural alternatives and conduct quantitative trade-off analysis\nDefine performance, power, capacity, bandwidth, latency, area, and cost targets\nAI Workload Characterization\nDevelop a deep understanding of the hardware implications of LLM inference, generative AI, agentic AI, long-context inference, KV-cache growth and management, retrieval-augmented generation (RAG), AI data movement and edge inference\nAnalyze workload bottlenecks and determine whether they are primarily caused by compute, memory capacity, memory bandwidth, latency, interconnect and software\nUse workload characterization to identify architectural opportunities\nInvestigate and architect new approaches to memory hierarchy and utilization, including HBM/DRAM tiering, CXL memory expansion, CXL memory pooling, memory disaggregation, intelligent caching, data placement, prefetching, memory compression, KV-cache management, model-weight storage, persistent and tiered memory and shared memory architectures\nMemory Hierarchy Innovation\nNear-Memory and In-Memory Computing\nInvestigate opportunities to reduce data movement by moving computation closer to memory. Potential areas include near-memory acceleration, processing-in-memory (PIM), memory-side computation, compression/decompression near memory, encryption/security processing, attention/KV-cache operations, embedding/vector operations and sparse computation\nDetermine which workloads can benefit sufficiently to justify dedicated hardware\nHardware / Software Co-Design\nWork closely with the AI Inference / Systems Software Architect to ensure that architectural features and hardware capabilities can be effectively exposed and utilized by the software stack. Collaborate on AI runtime architecture, memory management, KV-cache management, scheduling, data placement, prefetching, compression, workload orchestration, APIs and software interfaces and hardware telemetry and monitoring\nEnsure that hardware innovations translate into measurable application-level benefits rather than isolated component-level benchmarks\nArchitecture Modeling and Prototyping\nBuild or direct architectural models and simulations to evaluate proposed architectures\nEstablish workload-driven benchmarks for AI training and inference\nQuantify performance, power, capacity, bandwidth, latency, and TCO improvements\nDevelop proof-of-concept implementations and prototypes\nWork with R&D teams to move promising architectures from concept to silicon or system prototype\nDefine technical specifications and validation methodologies\nProduct Definition and Technical Roadmap\nWork with the AI Product Strategist and Chief AI System Architect to translate customer problems into product architectures. Contribute to Product requirements, System specifications, Architecture specifications, Performance targets, Technical differentiation, Product roadmap, Build-versus-buy decisions and Technology readiness assessment\nProvide technical leadership from initial concept through product definition and development\nWork with product strategy and executive management to do technical due diligence and evaluate emerging technologies, startup companies, intellectual property, licensing opportunities, strategic investments and acquisition candidates\nStrategic Technology Evaluation and M&A\nWork with product strategy and executive management to do technical due diligence and evaluate emerging technologies, startup companies, intellectual property, licensing opportunities, strategic investments and acquisition candidates\nRequired Qualifications:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field; PhD is a plus\n10+ years of experience in computer architecture, memory systems, semiconductor design, AI hardware, or related areas\nDeep understanding of modern computer architecture and memory hierarchy\nStrong experience with one or more of HBM, DDR, CXL, PCIe, UCIe, High-speed interconnect and AI accelerator architectures\nStrong understanding of AI/ML workloads and their architectural implications\nExperience performing quantitative architecture trade-off analysis\nExperience translating system requirements into hardware architecture and specifications\nDemonstrated experience contributing to or leading the development of complex semiconductor or computing systems\nStrong understanding of performance, power, area, bandwidth, latency, and cost trade-offs\nExcellent communication and technical leadership skills\nPreferred Qualifications:\nExperience with several of the following:\nLLM inference architecture\nKV-cache systems\nTransformer architectures\nCUDA / GPU architecture\nvLLM or other inference runtimes\nMemory compression\nCXL 2.x / 3.x or later\nCXL switching and pooling\nMemory disaggregation\nProcessing-in-memory\nNear-memory computing\nAI networking\nStorage-class memory\nASIC / SoC architecture\nRTL / microarchitecture\nArchitectural simulation and performance modeling\nHardware/software co-design\nEdge AI systems\nSalary Range: $285,000","description_format":"text","description_chars":7231,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Digital Storage","Memory & Storage Chips"],"lifecycle":[{"event":"open","at":"2026-11-12T23:00:47Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring 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