{"id":6193,"url":"https://alion.io/job/neuralink-hardware-software-co-design-engineer","title":"Hardware/ Software Co-Design Engineer","company":{"id":8,"name":"Neuralink","domain":"neuralink.com","url":"https://alion.io/company/neuralink","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":74,"open_postings":73,"ghost_share":0.356,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":141,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Fremont, United States","South San Francisco, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":151000,"max":261000,"currency":"USD","period":"year","gross":null,"usd_annual":261000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"Rust","optional":false},{"name":"SystemVerilog","optional":false},{"name":"SystemC","optional":true}],"status":"live","first_seen_at":"2026-02-20T00:50:25Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-16T23:51:34Z","board_verified":true,"closed_at":null,"days_open":239,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":238},"description":"About Neuralink:\nWe are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.\nTeam Description: \nThe Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. \nJob Description & Responsibilities: \nOur Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred.\nMicro-architecture design and RTL implementation of: \nLow-power digital signal processors\nLow-power general-purpose hardware accelerators\nLow-power graphics processing units\nLow-power radio MAC/PHY\nLow-power serial link MAC/PHY\nDesign and optimization of hardware/software interface with firmware engineers\nApplication-specific architecture optimization including:\nComplex system modeling for energy and performance benchmarks\nWorkload analysis and modeling\nEnergy/performance profiling and analysis\nLeveraging architecture-level design trade-offs with process technology and workload type\nBalancing cost and performance under manufacturing process variation \nCollaboration on silicon bring-up tests with verification engineers \nRequired Qualifications:\nBachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience\nEvidence of exceptional ability in electrical engineering, computer science, or computer engineering\nExperience designing and implementing embedded software in C or Rust\nExpertise in SystemVerilog, C/C++, Python\nExperience designing and implementing emulation models, transactors, and test environments to replicate hardware behavior\nExperience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools\nExperience in designing digital signal processing pipelines, from algorithm to RTL\nPreferred Qualifications: \nExperience in architecture optimization with process technology customization\nExperience in the verification of complex digital systems, using industry standard tools\nExperience in the physical design of complex digital systems, using industry standard tools\nExperience testing and debugging digital system-on-a-chips\nFunctional modeling experience and logic verification with SystemVerilog, SystemC/C++\nExperience automating tool flows\nExperience in processor instruction set architecture design\nExperience in compiler back-end design and customization\nExpected Compensation:\nThe anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.\nBase Salary Range:\n$151,000—$261,000 USD\nWhat We Offer:\nFull-time employees are eligible for the following benefits listed below.\nAn opportunity to change the world and work with some of the smartest and most talented experts from different fields\nGrowth potential; we rapidly advance team members who have an outsized impact\nExcellent medical, dental, and vision insurance through a PPO plan\nPaid holidays\nCommuter benefits\nMeals provided\nEquity (RSUs) *Temporary Employees & Interns excluded\n401(k) plan *Interns initially excluded until they work 1,000 hours\nParental leave *Temporary Employees & Interns excluded\nFlexible time off *Temporary Employees & Interns excluded","description_format":"text","description_chars":4373,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Flexible time off","Parental leave","Restricted stock units","Vision insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Medical & Healthcare Robotics","Neurotech & Neuromodulation"],"lifecycle":[{"event":"open","at":"2026-02-20T00:50:25Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 25 · green card filings: 1","filings_12m":25,"filings_prev_12m":12,"green_card_filings_12m":1,"median_offered_wage_usd":145962,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":5}],"liveness":{"score":17,"band":"cold","label":"Long shot","p_open":1,"p_active":0.484,"p_room":0.36,"age_days":238,"expected_fill_days":141,"reasons":["conf:3","velocity","win:tail","crowd:"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":261000,"is_top_pay":true},"html_url":"https://alion.io/job/neuralink-hardware-software-co-design-engineer","json_url":"https://alion.io/job/neuralink-hardware-software-co-design-engineer.json","meta":{"generated_at":"2026-10-17T03:40:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4796,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":8},"rest":"https://alion.io/mcp/rest/get_company?id=8"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fneuralink-hardware-software-co-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fneuralink-hardware-software-co-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fneuralink-hardware-software-co-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/neuralink-hardware-software-co-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fneuralink-hardware-software-co-design-engineer"}]}