{"id":1578804,"url":"https://alion.io/job/neurealm-principal-lead-rtl-design-engineer","title":"Principal/Lead RTL Design Engineer - ASIC/SoC","company":{"id":59455,"name":"Neurealm","domain":"neurealm.com","url":"https://alion.io/company/neurealm","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Kochi, India","Chennai, India","Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":58000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-10-01T11:32:15Z","employer_posted_date":null,"last_verified_at":"2026-10-01T11:32:15Z","board_verified":false,"closed_at":null,"days_open":33,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":33},"description":"Role : Principal / Lead RTL Design Engineer\n\nAbout the Role : \n\nWe are looking for a highly experienced Principal / Lead RTL Design Engineer to provide technical leadership for complex ARM-based ASIC/SoC development programs. The role involves driving RTL architecture and implementation, owning critical subsystems, defining design methodologies, and providing technical direction across the complete design lifecycle.\n\nKey Responsibilities : \n\n- Provide technical leadership for RTL architecture, design, and implementation of complex ASIC/SoC projects.\n\n- Own and drive design of critical IP blocks, subsystems, and SoC components from architecture through implementation.\n\n- Translate high-level system and micro-architectural specifications into optimized and scalable RTL.\n\n- Lead integration of ARM core-based designs into complex SoC architectures.\n\n- Define and drive implementation of AMBA AXI, AHB, and APB interfaces and interconnects.\n\n- Review and optimize RTL for performance, power, area, scalability, and design quality.\n\n- Establish and enforce RTL coding standards, design methodologies, and review processes.\n\n- Lead Lint and CDC closure across critical designs and subsystems.\n\n- Drive ASIC synthesis, Static Timing Analysis, timing closure, and design optimization.\n\n- Analyze and resolve complex timing and implementation challenges in collaboration with physical design teams.\n\n- Drive formal/equivalency checking and ensure design consistency across implementation stages.\n\n- Provide technical direction for FPGA prototyping and FPGA-based development where required.\n\n- Lead complex RTL debugging and root-cause analysis across design and integration environments.\n\n- Collaborate with architecture, verification, physical design, firmware, and system engineering teams.\n\n- Conduct design and code reviews and provide technical guidance to senior engineers.\n\n- Mentor engineers and establish best practices for RTL development and SoC integration.\n\n- Identify technical risks, dependencies, and design bottlenecks and drive their resolution.\n\n- Contribute to project planning, technical estimation, resource planning, and milestone execution.\n\n- Drive continuous improvement of RTL design methodologies, automation, and design quality.\n\nRequired Skills : \n\n- 15 - 18 years of experience in RTL Design / ASIC / SoC Design.\n\n- Expert-level proficiency in Verilog/VHDL and RTL design methodologies.\n\n- Deep expertise in ARM-based SoC architecture and integration.\n\n- Extensive experience with AMBA AXI, AHB, and APB protocols.\n\n- Strong expertise in Lint, CDC, ASIC synthesis, and Static Timing Analysis.\n\n- Extensive experience with formal/equivalency checking.\n\n- Strong experience in FPGA design and/or FPGA prototyping.\n\n- Deep understanding of digital architecture, microarchitecture, SoC integration, and design closure.\n\n- Strong expertise in debugging complex RTL and system-level design issues.\n\n- Proven ability to technically lead complex design projects and mentor senior engineers.\n\n- Strong cross-functional communication and stakeholder management skills.\n\nPreferred Skills : \n\n- Experience architecting and implementing complex ARM-based SoCs.\n\n- Experience with high-performance, high-speed, or power-sensitive designs.\n\n- Strong understanding of PPA optimization and timing closure.\n\n- Experience leading design methodology and process improvements.\n\n- Experience working with geographically distributed engineering teams.\n\n- Strong technical leadership and problem-solving capabilities.\n\nSkills\nRTL, ASIC, SoC, Verilog, ARM, VHDL, Static Timing Analysis, Synthesis","description_format":"text","description_chars":3605,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Artificial Intelligence","Information Technology","AI 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