{"id":1578801,"url":"https://alion.io/job/neurealm-senior-design-verification-engineerlead","title":"Senior Design Verification Engineer/Lead","company":{"id":59455,"name":"Neurealm","domain":"neurealm.com","url":"https://alion.io/company/neurealm","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Kochi, India","Chennai, India","Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":60000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Linux","optional":true},{"name":"Unix","optional":true}],"status":"live","first_seen_at":"2026-10-01T11:35:28Z","employer_posted_date":null,"last_verified_at":"2026-10-01T11:35:28Z","board_verified":false,"closed_at":null,"days_open":19,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":19},"description":"Senior Design Verification Engineer / Lead\n\nExperience : 9 - 14 Years\n\nLocation : Bangalore / Kochi / Chennai / Pune\n\nJob Type : Full-time\n\nAbout the Role : \n\nWe are seeking an experienced Senior Design Verification Engineer / Lead to drive verification activities for complex IP/SoC projects. The role requires strong hands-on expertise in SystemVerilog, UVM, AMBA protocols, ARM CPU verification, and verification environment architecture, along with the ability to independently own verification deliverables.\n\nKey Responsibilities : \n\n- Own verification strategy and execution for complex IP, subsystem, or SoC-level projects.\n\n- Architect, develop, and enhance scalable SystemVerilog/UVM verification environments.\n\n- Define verification plans, test strategies, coverage goals, and regression methodologies.\n\n- Develop reusable verification components including monitors, drivers, scoreboards, checkers, sequences, and assertions.\n\n- Drive constrained-random verification, functional coverage, code coverage, and coverage closure.\n\n- Lead verification of AMBA protocols and ARM CPU-based systems.\n\n- Work on PCI Express and/or Ethernet protocol verification as required.\n\n- Analyze complex failures and lead root-cause debugging across RTL, testbench, and system-level environments.\n\n- Collaborate closely with RTL designers, architects, firmware, validation, and system teams.\n\n- Identify verification gaps and introduce automation and process improvements.\n\n- Develop automation frameworks and utilities using Python, Perl, Shell, and Makefile.\n\n- Review verification code, test plans, coverage reports, and debug methodologies.\n\n- Mentor junior and mid-level verification engineers.\n\n- Track project progress, risks, bugs, coverage, and verification sign-off criteria.\n\nRequired Skills : \n\n- 9 - 14 years of hands-on experience in Design Verification.\n\n- Strong expertise in SystemVerilog and UVM.\n\n- Proven experience architecting and implementing functional verification environments.\n\n- Strong knowledge of AMBA protocols and ARM CPU architecture.\n\n- Experience with PCIe and/or Ethernet protocols is highly desirable.\n\n- Strong understanding of constrained-random verification, assertions, functional coverage, and coverage closure.\n\n- Excellent debugging and root-cause analysis capabilities.\n\n- Strong Unix/Linux experience.\n\n- Experience with configuration management, bug tracking, regression, and verification dashboarding tools.\n\n- Strong scripting/automation skills using Python, Perl, Shell, and/or Makefile.\n\n- Ability to independently drive verification milestones and deliverables.\n\nPreferred Skills : \n\n- Experience in complex SoC, CPU, subsystem, or high-speed interface verification.\n\n- Experience defining verification architecture and methodology for new projects.\n\n- Exposure to formal verification or other advanced verification methodologies.\n\n- Strong code review and mentoring experience.\n\n- Excellent communication and cross-functional collaboration skills\nSkills\nUVM, AMBA, ARM, Python, Perl, Verification, System Verilog, PCI-e, Design Verification","description_format":"text","description_chars":3084,"description_truncated":false,"requirements":{"experience_years_min":9,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Information Technology","IT Outsourcing & Dedicated Teams","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-01T12:00:00Z"}],"visa":[],"liveness":{"score":52,"band":"ok","label":"Likely open","p_open":0.85,"p_active":0.811,"p_room":0.75,"age_days":18,"expected_fill_days":26,"reasons":["seen:18","velocity","win:late"],"computed_at":"2026-10-20T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/neurealm-senior-design-verification-engineerlead","json_url":"https://alion.io/job/neurealm-senior-design-verification-engineerlead.json","meta":{"generated_at":"2026-10-20T13:06:10Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14506,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-21T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":59455},"rest":"https://alion.io/mcp/rest/get_company?id=59455"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fneurealm-senior-design-verification-engineerlead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fneurealm-senior-design-verification-engineerlead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fneurealm-senior-design-verification-engineerlead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/neurealm-senior-design-verification-engineerlead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fneurealm-senior-design-verification-engineerlead"}]}