{"id":1578808,"url":"https://alion.io/job/neurealm-senior-dft-engineerlead","title":"Senior DFT Engineer/Lead","company":{"id":59455,"name":"Neurealm","domain":"neurealm.com","url":"https://alion.io/company/neurealm","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India","Kochi, India","Chennai, India","Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":52000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":10},"experience_years_min":9,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Cadence Allegro","optional":true}],"status":"live","first_seen_at":"2026-10-01T11:26:25Z","employer_posted_date":null,"last_verified_at":"2026-10-01T11:26:25Z","board_verified":false,"closed_at":null,"days_open":16,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":16},"description":"Job Title : Senior DFT Engineer / Lead\n\nExperience : 9-14 Years\n\nLocation : Bangalore / Kochi / Chennai / Pune\n\nEmployment Type : Full-time\n\nAbout the Role :\n\nWe are seeking an experienced Senior DFT Engineer / Lead to drive DFT implementation, ATPG, coverage closure, MBIST, and test architecture activities for complex ASIC/SoC designs.\n\nThe candidate should be capable of independently owning DFT blocks and flows while collaborating with design, verification, synthesis, and ATE teams.\n\nKey Responsibilities :\n\n- Own DFT implementation activities across complex ASIC/SoC designs.\n\n- Drive scan architecture, scan insertion, ATPG generation, and coverage closure.\n\n- Generate and analyze ATPG patterns for Stuck-At and At-Speed fault models.\n\n- Analyze test coverage and implement strategies to improve coverage and test quality.\n\n- Lead MBIST insertion, configuration, simulation, and debug.\n\n- Implement and validate Boundary Scan, TAP Controller, and IEEE 1500/P1500 structures.\n\n- Drive both RTL-based and netlist-based DFT insertion flows.\n\n- Perform DFT simulations with and without SDF and debug complex simulation failures.\n\n- Work with synthesis and formal verification teams to ensure DFT implementation correctness.\n\n- Support DC characterization and associated test requirements.\n\n- Generate TDL patterns/data for ATE and work closely with ATE teams during bring-up.\n\n- Support silicon bring-up and debug test-related issues.\n\n- Work with DFT tools from Mentor/Siemens EDA, Synopsys, and Cadence.\n\n- Develop automation scripts using Perl and TCL to improve DFT productivity.\n\n- Perform and review Static Timing Analysis for DFT-related paths where required.\n\n- Collaborate with RTL, physical design, STA, verification, ATE, and product engineering teams.\n\n- Mentor junior DFT engineers and contribute to DFT methodology and flow improvements.\n\nRequired Skills :\n\n- 9-14 years of strong experience in DFT / ASIC / SoC Test.\n\n- Extensive hands-on experience with Scan insertion and ATPG.\n\n- Strong expertise in Stuck-At and At-Speed fault models and coverage analysis.\n\n- Strong experience with MBIST insertion and simulation.\n\n- Experience with Boundary Scan, TAP Controller, and IEEE 1500/P1500.\n\n- Strong knowledge of RTL and netlist-based DFT insertion flows.\n\n- Experience with DFT simulation with and without SDF.\n\n- Good understanding of synthesis and formal verification tools.\n\n- Experience with ATE/TDL generation and silicon bring-up.\n\n- Strong scripting skills in Perl and TCL.\n\n- Hands-on experience with DFT tools from Mentor/Siemens EDA, Synopsys, and Cadence.\n\n- Good understanding of Static Timing Analysis.\n\n- Strong debugging, problem-solving, and communication skills.\n\nPreferred Skills :\n\n- Experience owning DFT implementation for complete blocks/subsystems.\n\n- Exposure to advanced-node SoC/ASIC designs.\n\n- Experience working directly with ATE and product engineering teams.\n\n- Experience developing or improving DFT flows and automation.\n\n- Mentoring and technical leadership experience\n\nSkills\nDFT, ATPG, SoC, MBIST, RTL, Physical Design, Cadence Allegro, Synopsys, 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