{"id":46438,"url":"https://alion.io/job/nexperia-mixed-signal-design-verification-msdv-engineer","title":"Mixed Signal Design Verification (MSDV) Engineer","company":{"id":4240,"name":"Nexperia","domain":"nexperia.com","url":"https://alion.io/company/nexperia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":85,"open_postings":10,"ghost_share":0,"stale_share":0.4,"repost_share":0,"time_to_fill_p50_days":65,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Dallas, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":93000,"max_usd":211000,"period":"year","method":"role_country_seniority_unknown","sample_n":2687},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Git","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Unix","optional":true},{"name":"UVM","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-08-07T00:00:00Z","employer_posted_date":"2026-08-07","last_verified_at":"2026-10-19T01:02:55Z","board_verified":true,"closed_at":null,"days_open":73,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":73},"description":"Mixed Signal Design Verification Engineer\nPosition Summary\nIntegrated Circuit Solutions (ICS) Group is seeking a highly motivated Mixed Signal Design Verification Engineer with a strong background in analog and mixed-signal IC design verification. In this role, you will be responsible for pre-tapeout verification of silicon design, ensuring the part will meet all stated specifications and behavior and is manufacturable and testable. Familiarity with power converters and the challenges of power design is a plus. This position requires strong communication skills and leadership qualities. The selected individual will assume a technical contributor role with the ability to identify and implement opportunities for continuous improvement and work collaboratively with a diverse team of analog and digital designers, layout engineers, and system architects to ensure first-pass silicon success and high-quality product delivery.\nKey Responsibilities\nOperate as DV lead to drive quality product tapeouts\nDevelop a detailed pre-Si verification plan, create simulation environments, and mixed-signal behavioral models and work closely with design and systems teams to execute automated regressions to ensure coverage goals are met\nInterface across different functional groups such as systems, applications, test, silicon validation, etc. to ensure product design was verified correctly and completely and that end-product fits customer’s needs\nBuild relationships with internal teams by closely interacting with them to identify and solve design related problems\nAnalyze simulation results, identify root causes of failures, and provide actionable recommendations.\nParticipate in design reviews, verification reviews, and silicon bring-up activities.\nSupport post-silicon validation and correlation between simulation and measured silicon performance.\nRequired Qualifications\nStrong familiarity with EDA design tools such as Cadance Virtuoso design environment\nStrong familiarity with analog, digital and mixed-signal design and tool flow\nExtensive experience with Verilog/Verilog-A/SystemVerilog and Universal Verification Methodology (UVM) to run automated regressions\nWorking knowledge of Unix shell, TCL, Perl, Python and SKILL scripting languages\nExcellent analytical, troubleshooting, and communication skills.\nBachelor’s, Master’s or PhD degrees in Electrical Engineering or related field of study\nPreferred Qualifications\nExperience developing verification environment for integrated circuits that incorporate I2C, PMBus or SPI type communication protocols\nUnderstand power management chip architectures (ideal diodes, e-fuses, switching converters etc)\nExperience with lab validation is a plus\nUnderstand ESD, reliability, and electro-migration verification\nExperience with semiconductor manufacturing processes and design-for-test methodologies.\nFamiliarity with version control systems such as DesignSync, SVN, Git.\nSuccess Factors\nThe ideal candidate is detail-oriented, analytical, and collaborative, with a passion for delivering robust analog and mixed-signal designs. They thrive in a fast-paced development environment, communicate effectively across cross-functional teams, and are committed to continuous improvement of verification methodologies.\nBenefits\nCompetitive salary and performance-based incentives\nComprehensive health, dental, and vision insurance\nRetirement savings plan with company match\nPaid time off and company holidays\nProfessional development and training opportunities\nCollaborative and innovative engineering environment\nOpportunities to work on cutting-edge semiconductor technologies\nAbout the team\nJoin a global team at the forefront of innovation and play a key role in shaping the future of Nexperia’s product offerings.\nNexperia is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, color, creed, religion, national origin, ancestry, citizenship status, age, sex or gender (including pregnancy, childbirth and pregnancy-related conditions), gender identity or expression (including transgender status), sexual orientation, marital status, military service and veteran status, physical or mental disability, genetic information, or any other characteristic protected by applicable federal, state or local laws and ordinances. Nexperia’s management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, TeamNexperian’s activities, access to facilities and programs and general treatment during employment.\nMore information?\nFor more details please contact: \nTalent acquisition based on Nexperia vacancies is not appreciated. Nexperia job adverts are Nexperia copyright © material and the word Nexperia® is a registered trademark.\nD&I Statement\nAs an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.\nIn addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women's groups. Nexperia is committed to increasing women in management positions to 30% by 2030.","description_format":"text","description_chars":5611,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Professional development","Retirement plans","Vision insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Semiconductor Manufacturing","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-08-07T00:00:00Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 3 · green card filings: 1","filings_12m":3,"filings_prev_12m":2,"green_card_filings_12m":1,"median_offered_wage_usd":151250,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":2}],"liveness":{"score":28,"band":"fade","label":"Fading","p_open":1,"p_active":0.63,"p_room":0.44,"age_days":73,"expected_fill_days":65,"reasons":["conf:4","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-19T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/nexperia-mixed-signal-design-verification-msdv-engineer","json_url":"https://alion.io/job/nexperia-mixed-signal-design-verification-msdv-engineer.json","meta":{"generated_at":"2026-10-19T16:54:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":12799,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4240},"rest":"https://alion.io/mcp/rest/get_company?id=4240"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnexperia-mixed-signal-design-verification-msdv-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnexperia-mixed-signal-design-verification-msdv-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnexperia-mixed-signal-design-verification-msdv-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nexperia-mixed-signal-design-verification-msdv-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnexperia-mixed-signal-design-verification-msdv-engineer"}]}