{"id":1247888,"url":"https://alion.io/job/nexthop-systems-senior-signal-integrity-engineer","title":"Senior Signal Integrity Engineer","company":{"id":1954274,"name":"Nexthop Systems","domain":"nexthop.ai","url":"https://alion.io/company/nexthop-ai","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"BambooHR","truth_index":{"grade":"C","score":64,"open_postings":35,"ghost_share":0.514,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":78,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":136000,"max_usd":248000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1396},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys SIwave","optional":false},{"name":"BERT","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-24T00:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-24T19:39:16Z","board_verified":true,"closed_at":null,"days_open":30,"trust":{"level":"ok","repost_count":0,"flags":["company_stale"],"days_open":30},"description":"At Nexthop AI, we are searching for an experienced Signal Integrity Engineer to own the high-speed channel design of our next-generation switch platforms. If you've spent your career finding out where the textbook answers stop working, and you want to do that at 224G PAM4 and beyond on hardware that ships, we'd love to have you on our team.\nAbout the Role\nAs a Senior Signal Integrity Engineer, you'll be the SI owner for a full platform, with links running at 224G PAM4 per lane and beyond - from concept-phase feasibility, through stackup freeze and design release, into EVT/DVT link bring-up and debug. You'll set the channel targets and loss budgets that the design is built to, drive stackup and material decisions with our fab partners, and be the person the team turns to when a channel doesn't close. You'll also shape the methodology and design rules the rest of the SI team works from, and mentor engineers earlier in their careers.\nWhat You'll Do\nOwn signal integrity end to end for one or more switch platforms: pre-layout feasibility, channel architecture, simulation sign-off at design release, and link-performance debug through EVT and DVT.\nSet high-speed channel targets and loss budgets for links at 224G PAM4 per lane and beyond, and defend them against ASIC SerDes capability, module requirements, and cost and manufacturability constraints.\nDrive the hardest interconnect problems: ASIC BGA escape design, connector launch optimization, via tuning at frequencies where via electrical length matters, sequential lamination and backdrill strategy, and cascade behavior across the full channel.\nOwn stackup and material strategy with PCB fab vendors - laminate selection, Dk/Df modeling, impedance and loss coupon coverage, multi-vendor alignment, and DFM closure.\nRun compliance and link analysis (COM, ERL, and the evolving IEEE 802.3dj metrics) for C2M and C2C channels across the module ecosystem we support.\nLead correlation between simulation, coupon data, and system measurement - VNA, TDR, high-speed scopes, BERT, and the ASIC's built-in SerDes diagnostics (internal eye scans, pre-FEC BER, equalizer settings) - and drive root cause when they disagree.\nWork directly with ASIC, connector, and package vendors on models, launch geometry, and specifications; hold them to what we need.\nImprove how the team works: simulation automation in Python, reusable analysis flows, routing and via design rules, and the SI requirements our hardware and layout partners design against.\nMentor junior SI engineers, review their analysis, and participate in hiring.\nWhat We're Looking For\nTechnical Expertise\nMS or PhD in Electrical Engineering, Physics, or a related field (BS with equivalent depth considered), with 10-15 years of signal integrity experience on high-speed system design.\nProven track record owning SI for complex boards through to production - ideally high pin-count, high-power ASIC designs at 50G/lane or above.\nDeep expertise in 3D EM simulation and extraction: HFSS, SIwave, Sigrity, ADS, or equivalent, including model correlation to measurement.\nCommand of differential and mixed-mode S-parameters, mode conversion, crosstalk attribution, and time-domain analysis - and the physics behind the anomalies.\nExperience with link budgeting and compliance methodology for high-speed Ethernet (COM, ERL, IEEE 802.3ck / 802.3dj or comparable), including C2M channel definition.\nHands-on knowledge of PCB stackup design, low-loss materials, and fabrication process capability and its variation.\nStrong Python skills for simulation automation and large-scale data analysis.\nNice to Have\n224G PAM4 / 200G-per-lane channel design experience.\nParticipation in IEEE 802.3 or OIF standards work.\nExperience with cabled and optical module ecosystems (OSFP, QSFP-DD, DAC/ACC/AEC/LPO/LRO).\nPower integrity or EMC breadth alongside SI.\nExperience building an SI methodology or team from an early stage.\nHands-On Skills\nDesigning and validating via and launch structures against measured data, not just simulation.\nHigh-speed measurement and de-embedding, including fixture design and calibration strategy.\nReading layout critically and giving layout and hardware engineers actionable, prioritized feedback.\nSoft Skills\nTakes ownership of outcomes, not just analyses - you close problems rather than reporting them.\nCan \"do what it takes to succeed\" and be a team player simultaneously.\nExceptional communication: able to explain a channel risk to an ASIC vendor, a layout engineer, and an executive on the same day.\nSound engineering judgment under schedule pressure, with a clear view of technical risk and tradeoffs.\nGenerous with what you know - you make the engineers around you better.\nLocation\nThis role is based in our Bay Area office. Platform ownership at Nexthop includes hands-on lab correlation and bring-up work, so we expect regular onsite presence.\nWhy Join Us?\nAt Nexthop AI, we believe in pushing boundaries and turning ideas into reality. You'll be a technical owner on products built for the largest AI deployments in the world, working at the edge of what copper interconnect can deliver, alongside a team that has shipped datacenter networking hardware at scale. The problems here don't have published answers yet. Let's build something extraordinary together.\nReady to make an impact?Apply now and take your career to the next level!","description_format":"text","description_chars":5376,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Servers & Data Center Hardware","Network Equipment"],"lifecycle":[{"event":"open","at":"2026-09-25T18:02:57Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 23","filings_12m":23,"filings_prev_12m":17,"green_card_filings_12m":0,"median_offered_wage_usd":202500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":10}],"liveness":{"score":55,"band":"ok","label":"Likely open","p_open":1,"p_active":0.607,"p_room":0.9,"age_days":30,"expected_fill_days":78,"reasons":["conf:1","stale_co","velocity","win:mid"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/nexthop-systems-senior-signal-integrity-engineer","json_url":"https://alion.io/job/nexthop-systems-senior-signal-integrity-engineer.json","meta":{"generated_at":"2026-10-24T23:13:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":34144,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1954274},"rest":"https://alion.io/mcp/rest/get_company?id=1954274"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnexthop-systems-senior-signal-integrity-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnexthop-systems-senior-signal-integrity-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnexthop-systems-senior-signal-integrity-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nexthop-systems-senior-signal-integrity-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnexthop-systems-senior-signal-integrity-engineer"}]}