{"id":196572,"url":"https://alion.io/job/nokia-soc-physical-design-engineer","title":"SoC Physical Design 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to drive feasibility studies and explore design trade-off for physical design closure\nPerform technical evaluations of IP vendors, process nodes and provide recommendations\nDevelop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII\nPerform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off\nPerform Physical verification and IR/EM analysis on blocks as well as top \n 3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes\nHas solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design\nExperience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like Redhawk\nScripting experience in TCL, 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