{"id":3870906,"url":"https://alion.io/job/nokia-student-intern-research","title":"Student Intern - Research","company":{"id":17345,"name":"Nokia","domain":"nokia.com","url":"https://alion.io/company/nokia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Oracle","truth_index":{"grade":"A","score":92,"open_postings":86,"ghost_share":0.035,"stale_share":0.36,"repost_share":0.151,"time_to_fill_p50_days":9,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"Verilog","optional":false},{"name":"Quantization","optional":true}],"status":"live","first_seen_at":"2026-11-06T07:36:33Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-07T15:49:35Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Join us as an Intern with Nokia Bell Labs in Bangalore. The Bell Labs Platform ASIC Research lab explores advanced computing architectures and algorithms for next-generation communication systems. In this internship, you will focus on enabling energy-efficient AI and wireless communication workloads through hardware-aware AI algorithms, neuromorphic computing, and domain-specific hardware acceleration, with potential exploration of RISC-V-based accelerators. You will work across AI/ML, wireless signal processing, energy-efficient computing, and hardware/software co-design, developing concepts and running experiments in Python and C. The work may also involve evaluating compute and energy-efficiency trade-offs and contributing to Verilog-based implementations, accelerator microarchitecture, or architecture design studies. You will work closely with Nokia Bell Labs researchers on early-stage research that could influence future intelligent and energy-efficient wireless systems.\nKey Responsibilities\nExplore research ideas related toenergy-efficient compute for AI-driven wireless communication systems.\nStudy and evaluateneuromorphic computing approachesand their applicability to wireless workloads.\nDevelop experimental prototypes, models, and benchmarks usingPython and C.\nExplore accelerator concepts, includingRISC-V-based acceleration, custom instruction extensions, or hardware/software co-design approaches.\nPotentially contribute toVerilog implementation, microarchitecture exploration, or architecture-level design and simulation.\nCompare conventional AI compute approaches with low-power, event-driven, approximate, or neuromorphic compute techniques. \n You have\nEnrolled in aPh.D. or MS Research programat the time of the internship.\nStrong background in one or more areas such as computer architecture, VLSI/digital design, AI/ML algorithms, wireless communications, signal processing, embedded systems or hardware/software co-design \nHands-on programming experience inPythonand/orC.\nAbility to design experiments, analyze results, and iterate on research ideas independently. \nStrong fundamentals in algorithms, digital systems, and performance/energy trade-off analysis. \nAvailability for a6-month internship.\nIt would be nice if you also have\nExposure toRISC-V architecture, instruction-set extensions, accelerator design, or processor microarchitecture.\nInterest or experience inneuromorphic computing, spiking neural networks, event-driven compute, or low-power AI.\nFamiliarity with energy-efficient computing techniques such as quantization, sparsity, approximate computing, pruning, or workload-specific acceleration. \nUnderstanding ofRTL design, hardware simulation, or FPGA/ASIC design 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