{"id":3064088,"url":"https://alion.io/job/normal-computing-dft-engineer","title":"Hardware Engineer, DFT","company":{"id":39034,"name":"Normal Computing","domain":"normalcomputing.com","url":"https://alion.io/company/normalcomputing","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":95,"open_postings":3,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":67,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mountain View, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":162000,"max_usd":306000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":5966},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"Synopsys TestMAX","optional":false},{"name":"Tessent","optional":false},{"name":"AI Agents","optional":true}],"status":"live","first_seen_at":"2026-10-22T05:49:03Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-25T22:52:25Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"Normal Computing | Build with Us\nNormal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.\nThe Role\nAs a Design-for-Test (DFT) Engineer at Normal, you will own the DFT architecture and implementation for our next-generation, physics-inspired ASICs, from early RTL design through tapeout and silicon bring-up. You will define and drive scan/ATPG, memory built-in self-test (MBIST), and boundary-scan strategies, working closely with RTL, verification, physical design, and silicon product engineering teams.\nThis is a hands-on technical leadership role with end-to-end ownership of silicon testability. You will establish DFT methodologies, guide external implementation partners, and ensure our designs are ready for manufacturing test. You’ll work on unconventional computing architectures where testability must be considered from the beginning, with the opportunity to shape the DFT infrastructure for an entirely new class of silicon.\nWhat You Will Own\nDFT Architecture: Define and own chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.\n\nImplementation & Integration: Drive DFT insertion and integration across RTL, synthesis, and physical design, ensuring testability requirements are met without compromising power, performance, or area.\n\nTest Coverage & Signoff: Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout.\n\nManufacturing Test Readiness: Partner with the Head of Silicon Product Engineering to deliver production-ready test patterns and test collateral to our manufacturing partners, and documentation for ATE integration, silicon bring-up, and diagnosis.\n\nMethodology & Tooling: Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools, supporting future ASIC programs.\n\nExternal Partner Collaboration: Define technical requirements, oversee contracted DFT work, and review deliverables to ensure quality and integration with Normal’s silicon development process.\n\nWhat Makes You a Great Fit\n7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.\n\nStrong hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.\n\nProven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs.\n\nProficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.\n\nSolid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.\n\nExperience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.\n\nStrong scripting skills in Python, Tcl, or similar languages.\n\nAbility to independently own DFT architecture, drive cross-functional technical decisions, and communicate effectively across design, verification, and product engineering teams.\n\nBonus Points\nExperience establishing DFT architecture and methodology from the ground up for a new ASIC program.\n\nFamiliarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques.\n\nExperience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement.\n\nExperience working with external DFT implementation partners or managing outsourced DFT deliverables.\n\nExposure to AI accelerators, memory-intensive architectures, or unconventional computing systems.\n\nExperience using AI-assisted or agentic tools to automate silicon design and verification workflows.\n\nEqual Employment Opportunity Statement\nNormal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.\nAccessibility Accommodations\nNormal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at .\nPrivacy Notice\nBy submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.","description_format":"text","description_chars":4873,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","EDA Software","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-22T07:19:08Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 1","filings_12m":1,"filings_prev_12m":3,"green_card_filings_12m":0,"median_offered_wage_usd":262500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":1}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":67,"reasons":["conf:1","velocity","win:early"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/normal-computing-dft-engineer","json_url":"https://alion.io/job/normal-computing-dft-engineer.json","meta":{"generated_at":"2026-10-25T23:32:23Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":33235,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39034},"rest":"https://alion.io/mcp/rest/get_company?id=39034"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnormal-computing-dft-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnormal-computing-dft-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnormal-computing-dft-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/normal-computing-dft-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnormal-computing-dft-engineer"}]}