{"id":3013220,"url":"https://alion.io/job/normal-computing-hardware-engineer-rtl-lead","title":"RTL Lead","company":{"id":39034,"name":"Normal Computing","domain":"normalcomputing.com","url":"https://alion.io/company/normalcomputing","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":95,"open_postings":3,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":67,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Mountain View, United States","New York, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":246000,"max_usd":467000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-10-21T13:52:51Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-23T06:45:54Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"Normal Computing | Build with Us\nNormal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.\nThe Role\nAs a Lead RTL Design Engineer at Normal, you will lead and own the design of the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.\nYou will lead and own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely with physical design to make sure the design meets area and timing constraints. As a Lead, you will help with hiring, create and refine the design methodology, organize the design team around schedule and track progress. Because Normal's chips are not standard accelerators, the Lead RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.\nThis role requires a seasoned engineer with a track record of driving key initiatives, energizing the RTL team, and fostering cross-functional alignment across architecture, verification, and physical design. The ideal candidate has successfully led silicon through tapeout sign-off, played an active role in RTL implementation and design closure, and thrives in a dynamic setting where system specifications evolve alongside architectural and design development.\nWhat You Will Own\nTeam Leadership: Organize and set the standard and high expectations for the RTL design team. Foster a collaborative and execution focused environment.\n\nRTL Design: Create and enforce RTL coding standards. Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.\n\nMicroarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.\n\nVerification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.\n\nPhysical Design Collaboration: Collaborate with physical design on timing closure, PPA optimization, floorplanning constraints, and DFT.\n\nDesign Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.\n\nTapeout & Bring-up: Support tapeout preparation, create tapeout criteria, signoff on tapeout readiness, and post-silicon bring-up as needed.\n\n What Makes You a Great Fit\nExperience leading an RTL design team through multiple tapeouts. This includes block and toplevel work.\n\nHands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route for multiple blocks and design.\n\nExperience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront\n\nStrong debugging instincts across simulation, waveforms, and formal counterexamples\n\nAbility to work directly with architects and physical designers\n\n Bonus Points\nExperience at an AI chip company where design and verification were tightly coupled\n\nExperience with multiple interface architectures, for example PCIe, Ethernet, and memory devices.\n\nFamiliarity with FPGAs\n\nExperience with AI-assisted RTL or EDA tooling in your design workflow\n\nExposure to physical design constraints, floorplanning, or timing-driven RTL development\n\nEqual Employment Opportunity Statement\nNormal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.\nAccessibility Accommodations\nNormal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at .\nPrivacy Notice\nBy submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.","description_format":"text","description_chars":4766,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","EDA Software","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T15:49:47Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 1","filings_12m":1,"filings_prev_12m":3,"green_card_filings_12m":0,"median_offered_wage_usd":262500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":1}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":67,"reasons":["conf:3","velocity","win:early"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/normal-computing-hardware-engineer-rtl-lead","json_url":"https://alion.io/job/normal-computing-hardware-engineer-rtl-lead.json","meta":{"generated_at":"2026-10-23T10:59:29Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":16700,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39034},"rest":"https://alion.io/mcp/rest/get_company?id=39034"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnormal-computing-hardware-engineer-rtl-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnormal-computing-hardware-engineer-rtl-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnormal-computing-hardware-engineer-rtl-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/normal-computing-hardware-engineer-rtl-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnormal-computing-hardware-engineer-rtl-lead"}]}