{"id":99845,"url":"https://alion.io/job/normalcomputing-hardware-engineer-fpga","title":"Hardware Engineer, FPGA","company":{"id":39034,"name":"Normal Computing","domain":"normalcomputing.com","url":"https://alion.io/company/normalcomputing","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":100,"open_postings":4,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":55,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["New York, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":250000,"max":340000,"currency":"USD","period":"year","gross":null,"usd_annual":340000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"SystemVerilog","optional":false},{"name":"VHDL","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"CI/CD","optional":true},{"name":"Cocotb","optional":true},{"name":"Docker","optional":true},{"name":"GitLab CI","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-08-11T22:31:57Z","employer_posted_date":"2026-10-14","last_verified_at":"2026-10-16T16:41:45Z","board_verified":true,"closed_at":null,"days_open":65,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":65},"description":"Normal Computing | Build with Us\nNormal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.\nThe Role\nValidating conventional silicon is a solved discipline. Validating silicon that computes with noise is not, and you will be the one who figures out how. As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development, and building the test infrastructure for post-silicon bring-up and characterization. Your scope spans the entire FPGA lifecycle: selecting hardware platforms, implementing complex RTL, debugging in the lab, and writing the software that drives it all, working daily with our silicon, EDA, and research teams.\nWhat You Will Own\nFPGA Platform Ownership: Lead the selection, procurement, and bring-up of FPGA prototyping platforms (e.g., HAPS, VCU118/VPK180-class boards, or custom hardware) for pre-silicon RTL validation and software development.\n\nRTL Implementation: Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs.\n\nIP Integration: Integrate in-house designs with third-party and vendor IP; serve as the expert on the AMD/Xilinx ecosystem (Vivado IP Integrator, transceivers, memory controllers).\n\nHigh-Speed Interfaces: Design, implement, and validate high-speed I/O with a focus on PCIe: our accelerators ship as PCIe cards in standard servers.\n\nPost-Silicon Validation: Build FPGA-based \"tester\" designs for silicon bring-up, device characterization, and automated test environments.\n\nHardware-Software Stack: Develop the software layer around the hardware: Python/C++ hardware abstraction, register-map generation, and automated build and regression flows.\n\nLab Debug: Root-cause complex timing and functional issues in real time using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization of high-speed links.\n\nWhat Makes You a Great Fit\nProven industry experience taking FPGA designs from RTL through timing closure to validated hardware, ideally in an ASIC prototyping, emulation, or high-growth hardware environment.\n\nExpert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog).\n\nHands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other common interfaces.\n\nStrong Python for automation, test, and build tooling.\n\nStrong board-level bring-up and lab debugging skills on real hardware.\n\nStartup mindset: you work independently, pivot quickly, and run at ambiguous problems that span hardware, software, and physics.\n\nBonus Points\nVerification frameworks like Cocotb or UVM\n\nExperience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows), or building real-time, sub-microsecond signal processing pipelines.\n\nMixed-signal ASIC exposure: digital front-ends, ADC/DAC interfaces, or analog compute.\n\nSERDES tuning and signal integrity fundamentals.\n\nCI/CD for hardware (GitLab CI, Docker-based build and test).\n\nEqual Employment Opportunity Statement\nNormal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.\nAccessibility Accommodations\nNormal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at .\nPrivacy Notice\nBy submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.","description_format":"text","description_chars":4388,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","EDA Software","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-11T22:31:57Z"},{"event":"close","at":"2026-09-17T23:25:42Z"},{"event":"reopen","at":"2026-10-14T06:15:21Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 1","filings_12m":1,"filings_prev_12m":3,"green_card_filings_12m":0,"median_offered_wage_usd":262500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":1}],"liveness":{"score":34,"band":"fade","label":"Fading","p_open":1,"p_active":0.62,"p_room":0.55,"age_days":65,"expected_fill_days":55,"reasons":["conf:2","win:tail"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":340000,"is_top_pay":true},"html_url":"https://alion.io/job/normalcomputing-hardware-engineer-fpga","json_url":"https://alion.io/job/normalcomputing-hardware-engineer-fpga.json","meta":{"generated_at":"2026-10-16T18:52:46Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4204,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39034},"rest":"https://alion.io/mcp/rest/get_company?id=39034"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnormalcomputing-hardware-engineer-fpga"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnormalcomputing-hardware-engineer-fpga"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnormalcomputing-hardware-engineer-fpga"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/normalcomputing-hardware-engineer-fpga\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnormalcomputing-hardware-engineer-fpga"}]}