{"id":99850,"url":"https://alion.io/job/normalcomputing-hardware-engineer-physical-design","title":"Hardware Engineer, Physical Design","company":{"id":39034,"name":"Normal Computing","domain":"normalcomputing.com","url":"https://alion.io/company/normalcomputing","size_band":"51-200","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":100,"open_postings":4,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":55,"computed_at":"2026-10-16T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["New York, United States","London, United Kingdom","Zurich, Switzerland"],"countries":["US","GB","CH"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":400000,"currency":"USD","period":"year","gross":null,"usd_annual":400000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Pegasus","optional":false},{"name":"Synopsys IC Compiler II","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"HPC","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-07-31T06:39:04Z","employer_posted_date":"2026-07-31","last_verified_at":"2026-10-16T16:41:45Z","board_verified":true,"closed_at":null,"days_open":77,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":77},"description":"Normal Computing | Build with Us\nNormal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.\nThe Role\nAs a Physical Design Engineer at Normal, you will own the end-to-end silicon realization path, taking complex architectures from synthesis and physical floorplanning all the way through timing signoff and GDSII tapeout. Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems, you will shape physical feasibility early in the design cycle by working shoulder-to-shoulder with RTL and architecture teams. You'll drive the full backend implementation flow-optimizing floorplanning, place-and-route (P&R), clock tree synthesis (CTS), static timing analysis (STA), and physical verification (DRC/LVS) to achieve aggressive power, performance, and area (PPA) targets.\nWe are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution. The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures.\nWhat You Will Own\nPhysical Implementation & Flow: Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).\n\nTiming Closure & STA: Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.\n\nPower, Area, and Signal Integrity: Drive physical optimization for power, performance, and area (PPA), as well as power integrity (IR/EM) and crosstalk analysis.\n\nPhysical Signoff & Verification: Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.\n\nDesign & Floorplan Reviews: Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro placement, pin assignments, and physical feasibility.\n\nTapeout & Post-Silicon Support: Create and execute tapeout checklists, manage final stream-out processes, and support post-silicon physical debugging and bring-up as needed.\n\nWhat Makes You a Great Fit\nTapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes.\n\nPD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure.\n\nBackend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations.\n\nCross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility.\n\nBonus Points\nExperience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles.\n\nExperience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration).\n\nHands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows.\n\nEqual Employment Opportunity Statement\nNormal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.\nAccessibility Accommodations\nNormal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at .\n Privacy Notice\nBy submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.","description_format":"text","description_chars":4558,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"United Kingdom","iso":"GB","kind":"country"},{"name":"Switzerland","iso":"CH","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","EDA Software","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-07-31T06:39:04Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 1","filings_12m":1,"filings_prev_12m":3,"green_card_filings_12m":0,"median_offered_wage_usd":262500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":1}],"liveness":{"score":28,"band":"fade","label":"Fading","p_open":1,"p_active":0.514,"p_room":0.55,"age_days":76,"expected_fill_days":55,"reasons":["conf:2","win:tail"],"computed_at":"2026-10-16T05:45:00Z"},"pay":{"stated_usd_annual":400000,"is_top_pay":true},"html_url":"https://alion.io/job/normalcomputing-hardware-engineer-physical-design","json_url":"https://alion.io/job/normalcomputing-hardware-engineer-physical-design.json","meta":{"generated_at":"2026-10-16T18:18:23Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3251,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-17T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":39034},"rest":"https://alion.io/mcp/rest/get_company?id=39034"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnormalcomputing-hardware-engineer-physical-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnormalcomputing-hardware-engineer-physical-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnormalcomputing-hardware-engineer-physical-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/normalcomputing-hardware-engineer-physical-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnormalcomputing-hardware-engineer-physical-design"}]}