{"id":2314699,"url":"https://alion.io/job/nuvacore-cpu-architecture-verification-engineer","title":"CPU Architecture Verification Engineer","company":{"id":4394072,"name":"NUVACORE","domain":"nuvacore.ai","url":"https://alion.io/company/nuvacore","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Bengaluru, India","Santa Clara, United States","Markham, Canada"],"countries":["US","IN","CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":140000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Rust","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-09-08T16:41:42Z","employer_posted_date":"2026-09-08","last_verified_at":"2026-10-13T03:00:25Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification - checking the CPU's behavior and architectural state against the architecture specification and a golden reference model - building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.\nTHE ROLE\nPlan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness - the CPU's behavior and architectural state versus the specification and a golden reference model.\n\nEnvironment Setup: Build, maintain, and scale robust verification environments - including co-simulation against the golden reference model - that compare architectural state end to end.\n\nTest & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.\n\nCoverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.\n\nCross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.\n\nREQUIREMENTS - MUST TO HAVE\nDegree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.\n\n15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.\n\nStrong knowledge of CPU architecture and micro-architecture - the instruction set, architectural state, exceptions, and privilege model - with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).\n\nHands-on functional verification: test plans, testbenches, checkers, and coverage.\n\nProficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).\n\nExperience writing and debugging tests in assembly for CPU verification.\n\nREQUIREMENTS - NICE TO HAVE\nArchitectural / instruction-set verification against a golden reference model.\n\nRandom instruction sequence (RIS) stimulus generation.\n\nExceptions, interrupts, privilege levels, and virtualization.\n\nConstrained-random verification and coverage-driven closure.\n\nAssertions and formal verification.\n\nEmulation/FPGA and silicon bring-up and debug (waveforms, trace).","description_format":"text","description_chars":2730,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Data Centers & Colocation","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-12T03:38:43Z"}],"visa":[],"liveness":{"score":75,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.838,"p_room":0.9,"age_days":33,"expected_fill_days":51,"reasons":["conf:3","win:mid"],"computed_at":"2026-10-12T06:55:09Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/nuvacore-cpu-architecture-verification-engineer","json_url":"https://alion.io/job/nuvacore-cpu-architecture-verification-engineer.json","meta":{"generated_at":"2026-10-13T03:03:26Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4613,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4394072},"rest":"https://alion.io/mcp/rest/get_company?id=4394072"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnuvacore-cpu-architecture-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnuvacore-cpu-architecture-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnuvacore-cpu-architecture-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nuvacore-cpu-architecture-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnuvacore-cpu-architecture-verification-engineer"}]}