{"id":2314693,"url":"https://alion.io/job/nuvacore-cpu-custom-library-and-memory-layout-lead","title":"CPU Custom Library and Memory Layout Lead","company":{"id":4394072,"name":"NUVACORE","domain":"nuvacore.ai","url":"https://alion.io/company/nuvacore","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":300000,"currency":"USD","period":"year","gross":null,"usd_annual":300000},"salary_estimate":null,"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys StarRC","optional":false}],"status":"live","first_seen_at":"2026-09-18T18:15:15Z","employer_posted_date":"2026-09-18","last_verified_at":"2026-10-13T17:21:28Z","board_verified":true,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.\nTHE ROLE\nAs a Custom Library and Memory Layout Lead, you will participate in the following :\nLead physical layout of custom library cells (flip-flops, clock-gating cells, level shifters, AOI cells) and custom memory arrays (bit cell arrays, sense amps, decoders, register files) at advanced process nodes - own layout prototyping of critical cells.\n\nOwn end-to-end layout closure: floorplanning, logic/SRAM place-and-route, DRC/LVS/antenna clean-up, parasitic extraction hand-off, and mitigation of layout-dependent effects (LDE).\n\nPartner with circuit design, Foundry/PDK, CAD, and DFT teams to co-optimize layout for PPA, manufacturability, and yield; validate IP on testchips.\n\nDefine and drive layout methodology and automation - including P-cell/script-based layout generation and DRC/LVS regression - to raise design efficiency and set team-wide best practices.\n\nManage layout vendors and contractors to scale layout execution across macro designs and cells - scoping work packages, setting quality/schedule targets, and reviewing deliverables for PPA, DRC/LVS, and methodology compliance.\n\nMINIMUM QUALIFICATIONS\nHold a BS or MS degree with 12+ years of experience in custom/standard-cell and/or memory layout at advanced CMOS nodes.\n\nHands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays - bit cells, sense amps, decoders - at advanced CMOS nodes.\n\nDeep knowledge of DRC/LVS/antenna rules, parasitic extraction, and layout-versus-schematic closure using industry-standard EDA tools (e.g. Virtuoso, Calibre, StarRC).\n\nStrong understanding of layout-dependent effects, matching and symmetry techniques, and their impact on circuit PPA and variation.\n\nExperience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements.\n\nStrong communication and collaboration skills, comfortable working directly with circuit design, foundry, and CAD partner teams.\n\nRelevant hands-on experience laying out designs in cutting-edge process technologies, preferably Gate-All-Around (GAA) nodes.\n\nREQUIREMENTS - PREFERRED\nExperience across the full custom layout flow - floorplanning, cell/bit-cell layout, P-cell/script-based automation, DRC/LVS signoff, and extraction hand-off.\n\nProficient in SKILL, Python, or Tcl to build and improve layout automation and DRC/LVS regression flows.\n\nTrack record delivering production-level standard cell and/or memory layouts through tape-out, with silicon-validated PPA in high-volume products.\n\nExperience with testchip layout development and DTCO partnering with foundries at leading-edge nodes.\n\nExperience managing external layout vendors/contractors - work scoping, quality/schedule tracking, and technical review - to scale capacity across macro and cell layout programs.\n\nExperience using Agentic AI tools for productivity and automation.","description_format":"text","description_chars":3138,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Data Centers & Colocation","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-12T03:38:43Z"}],"visa":[],"liveness":{"score":58,"band":"ok","label":"Likely open","p_open":1,"p_active":0.77,"p_room":0.75,"age_days":24,"expected_fill_days":34,"reasons":["conf:2","win:late"],"computed_at":"2026-10-13T05:45:00Z"},"pay":{"stated_usd_annual":300000,"is_top_pay":true},"html_url":"https://alion.io/job/nuvacore-cpu-custom-library-and-memory-layout-lead","json_url":"https://alion.io/job/nuvacore-cpu-custom-library-and-memory-layout-lead.json","meta":{"generated_at":"2026-10-13T20:44:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":31816,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4394072},"rest":"https://alion.io/mcp/rest/get_company?id=4394072"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnuvacore-cpu-custom-library-and-memory-layout-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnuvacore-cpu-custom-library-and-memory-layout-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnuvacore-cpu-custom-library-and-memory-layout-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nuvacore-cpu-custom-library-and-memory-layout-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnuvacore-cpu-custom-library-and-memory-layout-lead"}]}