{"id":2314692,"url":"https://alion.io/job/nuvacore-cpu-custom-memory-design-srams-and-register-files","title":"CPU Custom Memory Design - SRAMs and Register Files","company":{"id":4394072,"name":"NUVACORE","domain":"nuvacore.ai","url":"https://alion.io/company/nuvacore","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":140000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-18T18:18:43Z","employer_posted_date":"2026-09-18","last_verified_at":"2026-10-22T22:24:38Z","board_verified":true,"closed_at":null,"days_open":34,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":34},"description":"Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.\nTHE ROLE\nAs a Custom Memory Design Engineer, you will participate in the following :\nOwn schematic development and characterize custom memories (SRAM, register files) to optimize PPA at advanced process nodes.\n\nSupervise layout implementation, defining macro floor planning, critical routing specifications, and driving physical design verification (PDV) closure.\n\nOwn end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization (timing, power, and noise in Liberty/CCS format) across PVT corners, meeting target PPA commitments.\n\nPartner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize custom memories for downstream design PPA.\n\nCollaborate closely with RTL, providing explicit custom memory functional specifications, timing behaviors, and state definitions to support accurate RTL modeling.\n\nDefine and drive adoption of Tools, Flows, and Methodology (TFM) - including characterization automation and compiler QA - to raise design efficiency and set team-wide best practices.\n\nMINIMUM QUALIFICATIONS\nHold a BS or MS degree with 8+ years of experience in custom memory circuit design : SRAMs, and/or Register files.\n\nHands-on transistor-level circuit design experience with combo cells, sequential logic in static/dynamic logic families, as well as memory arrays - bit cells, sense amps, decoders - in advanced CMOS nodes.\n\nDeep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cell architectures.\n\nProficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom memory design workflows.\n\nDemonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.\n\nDeep understanding of end-to-end signoff for custom memories - DRC/LVS/antenna, extraction, SPICE margins, STA, EM/IR - and characterization flows spanning timing, power, and noise.\n\nWell-versed in STA and Liberty/CCS lib model development and correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.\n\nStrong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.\n\nREQUIREMENTS - PREFERRED\nSubstantial experience across the full embedded memory design flow - architecture, circuit design, physical implementation, compiler automation, characterization, and timing/model generation.\n\nExperience designing and optimizing complex memory sub-blocks (self timed design tracking loops, read/write assist schemes, power-gating headers) and translating PDK device characteristics into cell/bit-cell circuit decisions.\n\nProven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.\n\nDemonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation (cosim) methods.\n\nExperience partnering directly with foundries on PDK bring-up and device co-optimization (DTCO) at leading-edge nodes.\n\nProficient in Python, Perl, or TCL to build and improve design, characterization, and QA automation.\n\nExperience using Agentic AI tools for productivity and automation.","description_format":"text","description_chars":3669,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Data Centers & Colocation","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-12T03:38:43Z"}],"visa":[],"liveness":{"score":56,"band":"ok","label":"Likely open","p_open":1,"p_active":0.751,"p_room":0.75,"age_days":33,"expected_fill_days":35,"reasons":["conf:1","velocity","win:late"],"computed_at":"2026-10-22T06:10:10Z"},"pay":{"stated_usd_annual":200000,"is_top_pay":true},"html_url":"https://alion.io/job/nuvacore-cpu-custom-memory-design-srams-and-register-files","json_url":"https://alion.io/job/nuvacore-cpu-custom-memory-design-srams-and-register-files.json","meta":{"generated_at":"2026-10-22T23:02:47Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8526,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4394072},"rest":"https://alion.io/mcp/rest/get_company?id=4394072"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnuvacore-cpu-custom-memory-design-srams-and-register-files"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnuvacore-cpu-custom-memory-design-srams-and-register-files"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnuvacore-cpu-custom-memory-design-srams-and-register-files"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nuvacore-cpu-custom-memory-design-srams-and-register-files\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnuvacore-cpu-custom-memory-design-srams-and-register-files"}]}