{"id":2314683,"url":"https://alion.io/job/nuvacore-cpu-design-verification-engineer-new-college-grad","title":"CPU Design & Verification Engineer — New College Grad","company":{"id":4394072,"name":"NUVACORE","domain":"nuvacore.ai","url":"https://alion.io/company/nuvacore","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":140000,"max":200000,"currency":"USD","period":"year","gross":null,"usd_annual":200000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-09-30T16:33:17Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-11-03T02:05:49Z","board_verified":true,"closed_at":null,"days_open":33,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":33},"description":"Nuvacore is building a ground-up, high-performance, low-power CPU for next-generation compute workloads. We are seeking new college graduates to join our CPU team, contributing to either Design Verification (DV) or RTL/micro-architecture design. You'll work shoulder-to-shoulder with architects, RTL designers, and verification engineers across units including fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and the multi-level cache subsystem - helping build and prove out a CPU that targets industry-leading power, performance, and area.\nTHE ROLE\nDepending on your interests and team placement, you'll contribute to one or both of the following:\nDesign Verification\nHelp build test plans, environments, stimulus generators, checkers, transactors, and coverage that exercise the CPU pipeline end to end.\nWrite and debug directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.\nPartner with architects to correlate RTL against performance models and help identify throughput, stall, and branch-prediction issues.\nContribute to functional coverage monitors and help analyze metrics toward test plan closure.\nWork with architecture and RTL teams to root-cause failures and support emulation, FPGA, and silicon bring-up.\nRTL / Micro-Architecture Design\nContribute to micro-architecture development, working with the performance modeling team to help converge early designs into detailed specifications.\nDevelop and refine RTL targeting power, performance, area, and timing goals.\nSupport verification efforts including testbench development, formal methods, and simulation/emulation.\nAssist in performance exploration and correlation, working with performance architecture and verification teams.\nCollaborate with the physical design team to help meet timing, power, area, DFT, and reliability goals.\nREQUIREMENTS - MUST HAVE\nBS or MS in Electrical/Computer Engineering, Computer Science, or equivalent practical experience (recent or upcoming graduate).\nCoursework or project experience in digital logic and computer architecture - pipelines, out-of-order execution, branch prediction, or similar topics.\nProficiency in C/C++, SystemVerilog, and/or Verilog, plus familiarity with a scripting language (Python preferred; Perl a plus).\nExposure to functional verification concepts (testbenches, checkers, coverage) or RTL design/coding, through coursework, internships, or personal projects.\nStrong fundamentals in CPU micro-architecture concepts.\nREQUIREMENTS - NICE TO HAVE\nInternship or project experience in CPU/complex digital design, verification, or RTL development.\nExposure to RISC-V, ARM64, or x86 ISA and their impact on micro-architectural choices.\nExperience with assembly-level programming or writing tests in assembly.\nFamiliarity with constrained-random verification, coverage-driven closure, or assertions/formal verification.\nExposure to emulation/FPGA environments, waveform debug, or silicon bring-up.\nInterest or coursework in one or more specialization areas: instruction fetch, branch prediction, decode/rename, out-of-order execution, load/store, cache and memory subsystems, memory coherence, or power management.\nStrong preference for being located at one of our main offices in Austin or Santa Clara","description_format":"text","description_chars":3414,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Data Centers & Colocation","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-12T03:38:43Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 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