{"id":2314698,"url":"https://alion.io/job/nuvacore-cpu-design-verification-lead","title":"CPU Design Verification Lead","company":{"id":4394072,"name":"NUVACORE","domain":"nuvacore.ai","url":"https://alion.io/company/nuvacore","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":140000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Assembly","optional":false},{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-09-18T05:12:02Z","employer_posted_date":"2026-09-18","last_verified_at":"2026-10-13T03:00:25Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. As Design Verification Lead you will lead the team verifying functionality and correctness of the CPU design. You will be responsible for all phases of pre-silicon verification as well as preparing for post-silicon verification.\nTHE ROLE\nAs a CPU Design Verification (DV) Lead, you will lead the team that is driving efforts in all the following areas:\nBuilding test environments which target every aspect of the CPU unit, core, or system. Your goal is to find every weakness and flaw in the design using proven verification techniques.\n\nDevelop methodology and flows for running simulations and generate all regression results and debug information.\n\nCreate test stimulus and relevant coverage metrics at both the unit and top level that fully stresses all corners of the design\n\nDevelop golden models and checkers at unit and top level as part of test bench infrastructure\n\nTriage issues and write up detailed bug reports to assist the CPU design team in fixing design issues.\n\nDevelop and write detailed test plans for the CPU units, core, or system.\n\nDevelop DV methodologies and best practices for the team.\n\nTest and debug the performance of a CPU against the performance model.\n\nWriting tests in ASM, C, C++, or other to test the CPU’s correctness according to the test plan\n\nLeverage formal methods and tools as another approach to determining design correctness\n\nVerification and testing of the gate level design of the CPU.\n\nSet up and leverage accelerated test environments such as emulation for high performance design testing\n\nMINIMUM QUALIFICATIONS\nBS or MS with 15+ years experience in CPU verification\n\nUnderstanding in architecture and design practices and the trade-offs in verifying CPU designs.\n\nExperience with one or more of RISC-V, ARM64, or x86 ISA\n\nStrong communication skills and aptitude in debugging and breaking things in CPUs\n\nExperience in C, C++, System Verilog, scripting and other languages such as Perl or Python\n\nExperience managing and mentoring DV engineers\n\nREQUIREMENTS - PREFERRED\nYears of expertise in multiple areas of CPU verification including unit level testing, top level testing, emulation, formal verification, coverage metrics\n\nExpertise in one or more areas of CPU microarchitecture including instruction fetch, branch prediction; instruction decoding, scheduling and register renaming; out-of-order execution; integer and floating point execution; load/store execution; prefetching; cache and memory subsystems; translation and memory management; memory coherence and ordering; power and thermal management; and clocking / reset design\n\nStrong background in low power microarchitecture and high-performance verification techniques, with a proven track record of verification and sign-off on multiple CPU programs.\n\nExperience managing large (20+) person design verification teams","description_format":"text","description_chars":2935,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Data Centers & Colocation","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-12T03:38:43Z"}],"visa":[],"liveness":{"score":70,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.781,"p_room":0.9,"age_days":24,"expected_fill_days":38,"reasons":["conf:3","win:mid"],"computed_at":"2026-10-12T06:55:09Z"},"pay":{"stated_usd_annual":250000,"is_top_pay":true},"html_url":"https://alion.io/job/nuvacore-cpu-design-verification-lead","json_url":"https://alion.io/job/nuvacore-cpu-design-verification-lead.json","meta":{"generated_at":"2026-10-13T03:43:38Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5961,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-14T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4394072},"rest":"https://alion.io/mcp/rest/get_company?id=4394072"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnuvacore-cpu-design-verification-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnuvacore-cpu-design-verification-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnuvacore-cpu-design-verification-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nuvacore-cpu-design-verification-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnuvacore-cpu-design-verification-lead"}]}