{"id":2314689,"url":"https://alion.io/job/nuvacore-cpu-micro-architect-rtl-lead-ic-engineers","title":"CPU Micro-Architect / RTL (Lead & IC Engineers)","company":{"id":4394072,"name":"NUVACORE","domain":"nuvacore.ai","url":"https://alion.io/company/nuvacore","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States","Santa Clara, United States","Canada"],"countries":["US","CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":140000,"max":300000,"currency":"USD","period":"year","gross":null,"usd_annual":300000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":false},{"name":"C++","optional":true},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-22T19:14:35Z","employer_posted_date":"2026-09-22","last_verified_at":"2026-10-15T19:48:12Z","board_verified":true,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":23},"description":"Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As engineers within the CPU team and as leads of CPU units (fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and multi-level cache subsystem), you will be writing specifications and developing RTL for the CPU which targets and delivers industry leading power, performance, and area.\nTHE ROLE\nAs a CPU Micro-Architect/RTL Engineer, you will participate in the following:\nMicro-architecture development and specification - starting from a performance driven design strategy, you will work with our performance modeling team and study early micro-architectures and converge on a design captured in a detailed specification. Critical understanding of the various pipelines and intra-unit communication will be necessary to build a clean yet performant design.\n\nRTL design - develop and refine RTL which targets the power, performance, area and timing goals. A solid understanding of the modern Verilog standards is a plus, enabling you to write RTL which is flexible and robust, configurable, and scalable.\n\nVerification - assist the verification team in all forms of CPU verification used, such as testbench development, formal methods, and simulation/emulation for formal verification\n\nPerformance exploration and correlation - explore high-performance strategies and work with the performance architecture and verification team to verify that the RTL meets targeted performance.\n\nPhysical design - work with the PD engineering team to implement and verify the physical design meets the goals. Be able to iterate and refine the RTL design. Incorporate improvements for timing, power, area, DFT, and reliability.\n\nREQUIREMENTS - MUST TO HAVE\nBS or MS with 15+ (leads) and 7+ (ICs) years experience in high-performance, low-power CPU design\n\nExperience with coding in Verilog, debugging, simulation, ideally with experience driving modern AI Tools to assist in RTL coding\n\nSolid understanding of logic and physical design and the impacts on timing, power, and area\n\nExperience with RISC-V or ARM64 or x86 ISA and their impacts on CPU micro-architectural choices\n\nREQUIREMENTS - NICE TO HAVE\nExpertise in one or more of the following areas: instruction fetch, branch prediction; instruction decoding, scheduling and register renaming; out-of-order execution; integer and floating point execution; load/store execution; prefetching; cache and memory subsystems; translation and memory management; memory coherence and ordering; power and thermal management; and clocking / reset design\n\nStrong background in low power microarchitecture and high-performance design techniques, with a proven track record of execution on multiple CPU programs and products\n\nExperience in C, C++, and other languages such as Perl or Python","description_format":"text","description_chars":2895,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"},{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Data Centers & Colocation","AI Agents"],"lifecycle":[{"event":"open","at":"2026-10-12T03:38:43Z"}],"visa":[],"liveness":{"score":72,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.805,"p_room":0.9,"age_days":22,"expected_fill_days":36,"reasons":["conf:1","velocity","win:mid"],"computed_at":"2026-10-15T05:46:00Z"},"pay":{"stated_usd_annual":300000,"is_top_pay":true},"html_url":"https://alion.io/job/nuvacore-cpu-micro-architect-rtl-lead-ic-engineers","json_url":"https://alion.io/job/nuvacore-cpu-micro-architect-rtl-lead-ic-engineers.json","meta":{"generated_at":"2026-10-15T20:53:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":31724,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-16T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4394072},"rest":"https://alion.io/mcp/rest/get_company?id=4394072"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnuvacore-cpu-micro-architect-rtl-lead-ic-engineers"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnuvacore-cpu-micro-architect-rtl-lead-ic-engineers"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnuvacore-cpu-micro-architect-rtl-lead-ic-engineers"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nuvacore-cpu-micro-architect-rtl-lead-ic-engineers\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnuvacore-cpu-micro-architect-rtl-lead-ic-engineers"}]}