{"id":3093421,"url":"https://alion.io/job/nvidia-asic-top-floorplan-intern-2027","title":"ASIC TOP Floorplan Intern, 2027","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":829,"ghost_share":0.023,"stale_share":0.739,"repost_share":0.042,"time_to_fill_p50_days":35,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-19T00:00:00Z","employer_posted_date":"2026-10-19","last_verified_at":"2026-10-24T08:48:21Z","board_verified":false,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"We are now looking for an Intern ASIC TOP Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.\nWhat you will be doing:\nWorking with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.\nDrive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.\nSolve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.\nYou will build tools and improve existing infrastructure to optimize chip area and speed of execution.\nWhat we need to see:\nMasters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work/learning experience.\nExperience in Verilog, System Verilog or similar HVL.\nExperience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.\nStrong communication and interpersonal skills and ability & desire to work as a great teammate should be displayed in your interview.\nPython, Perl and C/C++ programming language experience.\nWays to stand out from the crowd:\nExperience in driving development of large scale ASIC floorplan is a huge plus.\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. Our products are leading the way with groundbreaking developments in Artificial Intelligence, Autonomous Driving, High-Performance Computing and Visualization. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? 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