{"id":3010835,"url":"https://alion.io/job/nvidia-dft-engineer","title":"DFT Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":813,"ghost_share":0.025,"stale_share":0.677,"repost_share":0.046,"time_to_fill_p50_days":36,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":61000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":5845},"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Machine Learning","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"Verification & Validation","optional":false}],"status":"live","first_seen_at":"2026-10-19T00:00:00Z","employer_posted_date":"2026-10-19","last_verified_at":"2026-10-28T09:11:28Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"NVIDIA is seeking a highly motivated DFT Engineer to join our silicon engineering team. In this role, you will work closely with Design, Test, CAD, and Silicon Engineering teams to validate and debug Design-for-Test (DFT) features in some of the industry's most advanced GPUs and SoCs.\nThis position offers an excellent opportunity to learn industry-leading DFT methodologies and contribute to cutting-edge products powering AI, accelerated computing, and next-generation platforms.\nWhat you'll be doing\nVerify DFT features and test infrastructures, including Scan, MBIST, JTAG, and related functionality.\nCollaborate with Design, Integration, CAD, and Test Engineering teams to define verification scope and test strategies.\nExecute verification and validation activities at the IP, subsystem, and full-chip levels.\nPerform RTL and gate-level debugging to identify and resolve design and test issues.\nGenerate and validate test patterns and support silicon bring-up and debug activities.\nImprove engineering productivity through scripting, automation, and workflow enhancements.\nSupport verification flow and methodology improvements.\nWhat we need to see\n1+ years of experience with an M.S. degree in Electrical Engineering, Electronics Engineering, Microelectronics, IC Design, or a closely related discipline.\nStrong understanding of digital circuits, computer architecture, and semiconductor design fundamentals.\nStrong analytical, problem-solving, and debugging skills.\nFamiliarity with RTL simulation and debug tools such as Verdi and VCS.\nBasic understanding of SoC architecture, including clocking, reset, power, and I/O concepts.\nProgramming or scripting experience with Python, Tcl, Perl, C, or C++.\nFluent verbal and written communication skills in English.\nStrong teamwork skills and willingness to learn in a fast-paced environment.\nWays to stand out from the crowd\nUnderstanding of DFT methodologies, including Scan, ATPG, MBIST, JTAG, and Boundary Scan.\nExperience with RTL or gate-level simulation and debugging.\nFamiliarity with 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