{"id":194413,"url":"https://alion.io/job/nvidia-formal-verification-engineer","title":"Formal Verification Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":592,"ghost_share":0.019,"stale_share":0.66,"repost_share":0.034,"time_to_fill_p50_days":33,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":46000,"max_usd":106000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":723},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence JasperGold","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys VC Formal","optional":false}],"status":"live","first_seen_at":"2026-08-27T00:00:00Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-10-17T12:37:36Z","board_verified":true,"closed_at":null,"days_open":51,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":51},"description":"The NVIDIA GPU clocks group is looking for excellent Senior Formal Verification engineers to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team to understand the clocking requirements for the chip. We also understand the physical restrictions being placed on the clocks by the backend teams. The GPU clocks group architects, designs and validates the clocks RTL. The complexity of clocks RTL has increased many folds to support our features that power our product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.\nWhat you’ll be doing:\nUnderstand key design behaviors from formal verification view to write clear test plans, and implement them using the latest formal techniques, including the development of environment assumptions, assertions and cover properties.\nDevelop abstraction models to overcome complexity challenges and obtain full proofs, or bounded proofs with sufficient coverage.\nDebug RTL to identify causes of failure scenarios and finish coverage sign-off.\nDrive tools to realize their best performance.\nContribute to flow and script development to improve team efficiency.\nWork with architects, designers and others to guarantee good deliverable quality. \n What we need to see:\nBS / MS in CS/CE/EE/Mathematics and related with 3+ years of ASIC verification experience. \nKnowledge of formal verification methodologies and techniques, preferable experience with Formal Verification Tools (e.g. Jasper Gold, VC Formal ).\nAble to implement abstraction techniques for effective verification.\nExcellent command of scripting using TCL, Perl, and Python.\nFamiliar with verification methodology, tools and flow in Unit/Sub-system/SOC level.\nExcellent interpersonal skills, able to effectively collaborate and work with members of a distributed team.\nWays to stand out from the crowd:\nExcellent analytical and problem-solving skills, quick understanding to complex design or experience in different verification methodologies is plus.\nStrong prior knowledge/experience in different protocols/data transmission verification is plus. \nFluent English (both written and spoken) and excellent communication skills. \nGood teamwork spirit, easy to cooperate with team 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