{"id":3611850,"url":"https://alion.io/job/nvidia-ip-manager-design-and-verification-networking","title":"IP Manager, Design and Verification - Networking","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":792,"ghost_share":0.023,"stale_share":0.573,"repost_share":0.044,"time_to_fill_p50_days":40,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"CI/CD","optional":false},{"name":"Formal Verification","optional":false},{"name":"HPC","optional":false},{"name":"NVLink","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-02T14:38:51Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-04T13:34:17Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"We are looking for an IP Manager to join NVIDIA’s Networking front-end design team! In this role, you will lead and manage a cluster of IP teams responsible for both design and design verification (DV) of complex hardware IP blocks across NVIDIA’s next-generation SmartNIC and DPU products. You will own the end-to-end delivery of IPs - from micro-architecture definition and RTL implementation through functional verification, lint/CDC/RDC closure, synthesis, and silicon readiness.\nWe are looking for someone who thrives on building high-performing teams, driving IP execution across multiple parallel projects, and partnering with architecture, SoC integration, physical design, software, and program management teams to deliver world-class silicon.\nWhat You’ll Be Doing:\nLead, mentor, and grow a team of design and verification engineers across a cluster of IP blocks. You will define team structure, hiring plans, and career development paths to build a strong, scalable organization.\nOwn the end-to-end execution of IP delivery - micro-architecture, RTL design, functional verification, coverage closure, assertions, formal verification, and synthesis handoff. You will set quality bars, review schedules, and drive milestone adherence across your IP cluster.\nDefine and drive verification strategies, test plans, coverage goals, and sign-off criteria for your IPs. Your team will develop UVM-based constrained-random and directed test environments, achieve functional and code coverage targets, and ensure robust regression infrastructure.\nPartner with architecture, SoC integration, physical design, DFT, firmware, and software teams to resolve cross-functional dependencies, close interface specifications, and ensure seamless IP integration. We will look to you to identify risks early, drive trade-off decisions, and align technical priorities across stakeholders.\nEstablish and improve design and verification methodologies, best practices, reuse strategies, and automation flows to increase team productivity and IP quality across tape-outs.\nWhat We Need To See:\nB.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.\n10+ years of experience in ASIC/SoC design or verification, including 2+ years in a people management or technical leadership role managing multi-engineer teams.\nStrong understanding of digital design fundamentals - RTL coding (Verilog/SystemVerilog), micro-architecture, timing, clocking, reset, power management, and synthesis constraints.\nStrong understanding of verification methodologies - e-specman/UVM, constrained-random verification, coverage-driven verification, assertions (SVA), and formal verification techniques.\nExperience managing IP delivery across the full lifecycle - specification, design, verification, synthesis handoff, and post-silicon support.\nDemonstrated ability to manage multiple IPs or projects in parallel, balancing resources, schedules, and quality trade-offs.\nExperience with EDA tools for simulation, lint, CDC, RDC, synthesis, and debug.\nAbility to communicate technical status, risks, and trade-offs clearly to engineering leadership and cross-functional partners.\nWays To Stand Out from the Crowd:\nExperience with high-speed interfaces such as PCIe, NVLink, HBM, DDR, or high-speed SerDes IP blocks.\nExperience building or scaling verification infrastructure - regression frameworks, coverage automation, CI/CD pipelines for hardware, or emulation/FPGA prototyping flows.\nHands-on experience with scripting and automation using Python, Perl, TCL, or shell scripting to improve team workflows.\nBackground in GPU, networking, or AI/HPC-related IP domains is a strong plus.\nWe support our people with competitive compensation, health and wellness programs, financial benefits, time away from work, family support, learning opportunities, and resources that help employees do their best work. Benefits may vary by location, role, and eligibility. NVIDIA is an equal opportunity employer. We are committed to creating an inclusive environment for all employees and applicants. We consider qualified applicants without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, disability, age, veteran status, or other protected status. We provide reasonable accommodations for applicants and employees with disabilities. If you need support during the application or interview process, please let our recruiting team know.","description_format":"text","description_chars":4472,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Wellness"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-02T14:38:51Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":40,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-11-04T06:34:25Z"},"pay":null,"html_url":"https://alion.io/job/nvidia-ip-manager-design-and-verification-networking","json_url":"https://alion.io/job/nvidia-ip-manager-design-and-verification-networking.json","meta":{"generated_at":"2026-11-04T14:59:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22727,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-05T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":6},"rest":"https://alion.io/mcp/rest/get_company?id=6"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnvidia-ip-manager-design-and-verification-networking"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnvidia-ip-manager-design-and-verification-networking"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnvidia-ip-manager-design-and-verification-networking"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nvidia-ip-manager-design-and-verification-networking\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnvidia-ip-manager-design-and-verification-networking"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3611850}},{"tool":"search_jobs","arguments":{"company":"nvidia.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3611850},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}