{"id":2716867,"url":"https://alion.io/job/nvidia-principal-solutions-architect-semiconductor-test","title":"Principal Solutions Architect – Semiconductor Test","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":592,"ghost_share":0.019,"stale_share":0.66,"repost_share":0.034,"time_to_fill_p50_days":33,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":216000,"max":345000,"currency":"USD","period":"year","gross":null,"usd_annual":345000},"salary_estimate":null,"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-06-01T00:00:00Z","employer_posted_date":"2026-06-01","last_verified_at":"2026-10-17T04:27:35Z","board_verified":true,"closed_at":null,"days_open":138,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":138},"description":"We are seeking a Staff/Principal Solutions Architect to define and lead the technical strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead the architectural vision for device testing from wafer probe to final package test. Your directive includes modernising test infrastructure, improving yield, and embedding data-driven intelligence throughout the test lifecycle. You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios.\nWhat You'll be doing:\nDefine the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families.\n\nLead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.\n\nEstablish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).\n\nServe as the senior liaison between build and test engineering for DFT architecture decisions - scan, BIST, JTAG, boundary scan, and embedded compression.\n\nInfluence SoC and IP build reviews to ensure testability, observability, and debug-ability\n\nDrive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.\n\nDefine and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.\n\nMentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation.\n\nEngage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions.\n\nWhat we need to see:\n15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.\n\nExtensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.\n\nSkilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.\n\nStrong background in DFT architectures - scan compression, MBIST, LBIST, JTAG, and related methodologies.\n\nExperience with mixed-signal, RF, or high-speed I/O test is highly valued.\n\nProficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).\n\nProven ability to lead multi-site technical initiatives involving multi-functional teams and influence without direct authority.\n\nMSEE, MSCE, MSCS, or related field (or equivalent experience).\n\nWays to stand out from the crowd\nExperience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.\n\nKnowledge of test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom).\n\nExposure to advanced packaging test challenges (2.5D/3D, chiplets, KGD).\n\nPrior engagement with SEMI standards committees or ATE vendor co-development programs.\n\nPh.D or equivalent experience in related field\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most thoughtful and dedicated people in the world working for us. Due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.\nYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 216,000 USD - 345,000 USD.You will also be eligible for equity and benefits.\nApplications for this job will be accepted at least until June 5, 2026.This posting is for an existing vacancy.\nNVIDIA uses AI tools in its recruiting processes.\nNVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.","description_format":"text","description_chars":4497,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-16T13:57:57Z"}],"visa":[],"liveness":{"score":8,"band":"cold","label":"Long shot","p_open":1,"p_active":0.302,"p_room":0.28,"age_days":138,"expected_fill_days":33,"reasons":["conf:1","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":345000,"is_top_pay":true},"html_url":"https://alion.io/job/nvidia-principal-solutions-architect-semiconductor-test","json_url":"https://alion.io/job/nvidia-principal-solutions-architect-semiconductor-test.json","meta":{"generated_at":"2026-10-17T06:02:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8277,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":6},"rest":"https://alion.io/mcp/rest/get_company?id=6"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnvidia-principal-solutions-architect-semiconductor-test"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnvidia-principal-solutions-architect-semiconductor-test"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnvidia-principal-solutions-architect-semiconductor-test"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nvidia-principal-solutions-architect-semiconductor-test\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnvidia-principal-solutions-architect-semiconductor-test"}]}