{"id":1427509,"url":"https://alion.io/job/nvidia-senior-analog-layout-design-engineer","title":"Senior Analog Layout Design Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":89,"open_postings":297,"ghost_share":0.02,"stale_share":0.367,"repost_share":0.04,"time_to_fill_p50_days":28,"computed_at":"2026-10-01T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yokneam, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":122000,"max_usd":281000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1198},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-28T00:00:00Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-01T00:24:56Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"NVIDIA Analog Layout design team is looking for a Senior Analog Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence.\nWhat you'll be doing:\nPerform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools\n\nYou will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.\n\nJob duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis\n\nWhat we need to see:\nYou will have a minimum of 5 years of relevant mask analog layout experience\n\nAn Electronics Practical Engineer certificate or a B.Sc. in Electrical Engineering\n\nProven understanding of analog circuit layout concepts in submicron CMOS and FinFet technologies - such as Operational Amplifiers and ADC/DACs.\n\nYou are an expert with Cadence custom circuit design tools - particularly Virtuoso\n\nExperience running and debugging DRC and LVS with verification tools such as ICV, Calibre\n\nYou can work effectively in a team, good interpersonal skills, enthusiasm and positive energy.\n\nWays to stand out in the crowd:\nProficiency in scripting languages like python, skill\n\nKnowledge of DRC and LVS checking flows, EM/IR tools, ability to customize DRC and LVS decks\n\nNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the securest silicon possible? If so, we want to hear from you. Come, join our ASIC Security team and help build the real-time, cost-effective computing platform driving our success across several exciting and quickly growing fields.","description_format":"text","description_chars":2494,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-29T00:12:32Z"}],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":28,"reasons":["conf:5","velocity","win:early","comp:brand"],"computed_at":"2026-10-01T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/nvidia-senior-analog-layout-design-engineer","json_url":"https://alion.io/job/nvidia-senior-analog-layout-design-engineer.json","meta":{"generated_at":"2026-10-01T18:25:29Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":772,"day_limit":5000,"remaining_today":4228,"minute_limit":60,"resets_at":"2026-10-02T00:00:00Z"}}}