{"id":4318772,"url":"https://alion.io/job/nvidia-senior-asic-design-efficiency-engineer-2","title":"Senior ASIC Design Efficiency Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":740,"ghost_share":0.023,"stale_share":0.618,"repost_share":0.053,"time_to_fill_p50_days":43,"computed_at":"2026-11-14T05:58:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Durham, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":136000,"max":218500,"currency":"USD","period":"year","gross":null,"usd_annual":218500},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-11-13T00:00:00Z","employer_posted_date":"2026-11-13","last_verified_at":"2026-11-14T17:57:29Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology-and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.\nWe are now looking for a Senior ASIC Design Efficiency Engineer! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Join our dynamic team today!\nWhat you'll be doing:\nUnderstand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.\nUse internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.\nDevelop innovative memory subsystem designs to extend the state of the art performance and power efficiency.\nCollaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.\nWhat we need to see:\nBS Degree in CompE, EE, CS, or equivalent experience\n5+ years of relevant industry experience\nWorking knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog\nStrong interpersonal skills are required along with the ability to work in a diverse product oriented team.\nWays to stand out from the crowd:\nStrong analytical thought process and outstanding debug skills along with strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML-based insights to both design and tools teams.\nExperience with caches, coherency, complex pipelines, arbiters, or interconnect networks\nInfrastructure development, use of AI to support design and verification development\nFamiliarity with RTL implementation of low-power techniques (e.g., clock gating, operand isolation, power gating strategies, multi-VT usage) and their trade-offs.\nExperience debugging RTL or gate-level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root-cause structures or scenarios.\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\nYour base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:136,000 USD - 218,500 USD for Level 3; and 168,000 USD - 264,500 USD for Level 4.\nYou will also be eligible for equity and benefits.\nApplications for this job will be accepted at least until November 17, 2026.This posting is for an existing vacancy.\nNVIDIA uses AI tools in its recruiting processes.\nNVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. 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