{"id":2042222,"url":"https://alion.io/job/nvidia-senior-full-chip-rtl-integration-engineer","title":"Senior Full-Chip RTL Integration Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"A","score":88,"open_postings":346,"ghost_share":0.014,"stale_share":0.434,"repost_share":0.032,"time_to_fill_p50_days":29,"computed_at":"2026-10-07T05:47:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States","Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":168000,"max":264500,"currency":"USD","period":"year","gross":null,"usd_annual":264500},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-07T18:18:28Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-10-08T01:15:38Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! We are looking for a Full-Chip RTL Integration Engineer to join our dynamic and growing FE-ASIC development team. In this role, you will be responsible for integrating complex IPs and subsystems into large-scale SoCs while ensuring design quality, verification readiness, and DFT compliance.\nYou will work closely with Architecture, Design, Verification, DFT, and Physical Design teams to deliver high-quality silicon products in a collaborative and fast-paced environment. If you are a problem solver and highly motivated individual searching for a collaborative and exciting role, join us today! We encourage applicants with a history of proven success working in a multicultural and diverse environment.\nWhat you'll be doing:\nLead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs, owning top-level connectivity, clocking, reset architecture, address mapping, and power domain integration.\nWork closely with Architecture, RTL Design, Verification, DFT, and Physical Design teams to drive system-level integration and design closure.\nPerform RTL quality checks including lint, CDC, RDC, synthesis, and connectivity validation.\nDevelop and carry out integration-level verification plans using SystemVerilog/UVM, debug simulation failures, and support functional coverage closure.\nCollaborate with DFT teams to integrate scan, MBIST, LBIST, JTAG, and other test structures, and review ATPG reports and fault coverage metrics to ensure testability requirements are met.\nSupport design signoff activities and ensure smooth handoff across implementation stages.\nDevelop automation and scripting solutions to improve integration, verification, and debug productivity.\n What we need to see:\nB.S. or M.S. in Electrical Engineering, Computer Engineering, or related field (or equivalent experience) with 8+ years of experience.\nStrong experience in ASIC/SoC RTL Integration.\nExcellent understanding of digital design fundamentals, SoC architecture, clocking, reset, and bus protocols.\nStrong verification knowledge with hands-on experience in SystemVerilog and UVM.\nAbility to independently verify block-level and integration-level designs.\nStrong understanding of DFT methodologies including Scan, ATPG, MBIST, LBIST, JTAG, and test compression techniques.\nExperience with lint, CDC, RDC, and design quality signoff flows.\nStrong debugging, analytical, and problem-solving skills.\nGood communication skills and ability to work effectively across multiple engineering teams.\n Ways to stand out from the crowd:\nExperience with large-scale SoC or full-chip integration, including high-speed interfaces, processor subsystems, memory controllers, and third-party IPs.\nExposure to Synopsys, Cadence, or Siemens DFT and verification tools.\nExperience with low-power design methodologies and UPF.\nProficiency in Python, Perl, Tcl, or Shell scripting, and a passion for improving engineering productivity through automation and AI-assisted development tools.\nAbility to bridge integration, verification, and DFT domains to solve complex system-level challenges and drive efficient design closure.\n.\nWidely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/\n#LI-Hybrid\nYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.\nApplications for this job will be accepted at least until October 11, 2026.This posting is for an existing vacancy.\nNVIDIA uses AI tools in its recruiting processes.\nNVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.","description_format":"text","description_chars":4377,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-07T18:18:28Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":29,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-10-08T02:47:58Z"},"pay":{"stated_usd_annual":264500,"is_top_pay":true},"html_url":"https://alion.io/job/nvidia-senior-full-chip-rtl-integration-engineer","json_url":"https://alion.io/job/nvidia-senior-full-chip-rtl-integration-engineer.json","meta":{"generated_at":"2026-10-08T02:47:58Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4884,"day_limit":5000,"remaining_today":116,"minute_limit":60,"resets_at":"2026-10-09T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":6},"rest":"https://alion.io/mcp/rest/get_company?id=6"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnvidia-senior-full-chip-rtl-integration-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnvidia-senior-full-chip-rtl-integration-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnvidia-senior-full-chip-rtl-integration-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nvidia-senior-full-chip-rtl-integration-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnvidia-senior-full-chip-rtl-integration-engineer"}]}