{"id":100168,"url":"https://alion.io/job/nvidia-senior-mask-design-engineer-hardware-2","title":"Senior Mask Design Engineer – Hardware","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":797,"ghost_share":0.025,"stale_share":0.55,"repost_share":0.055,"time_to_fill_p50_days":41,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Semiconductors","role_family":"Semiconductors","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":34000,"max_usd":67000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":107},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-08-19T00:00:00Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-11-09T11:43:05Z","board_verified":true,"closed_at":null,"days_open":82,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":82},"description":"NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions!\nThis position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues.\nWhat you'll be doing:\nYou'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.\n\nPerforming physical layout for silicon interposer using Cadence tools.\n\nConduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.\n\nTake part in studying layout floorplan and perform custom layout and verification against design rules and netlists.\n\nPropose layout design trade-offs to the PTL for resolution and implementation.\n\nWhat we need to see:\nHold a B.S. Electrical Engineering or equivalent experience\n\nMinimum of 5+ years proven experience in Mask and Layout Design.\n\nDeep understanding of layout concepts in submicron CMOS technologies.\n\nYou are an authority with Cadence layout tools - particularly Virtuoso.\n\nKnowledge of Integrity auto-routing is a plus.\n\nExperience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.\n\nProficient in scripting languages like Perl, Python, Skill, etc.\n\nShould have knowledge of DRC and LVS checking flows, ability to customize decks. Knowledge of APD package layout tool is a plus.\n\nWith competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. 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