{"id":2736170,"url":"https://alion.io/job/nvidia-senior-memory-mask-design-engineer","title":"Senior Memory Mask Design Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":592,"ghost_share":0.019,"stale_share":0.66,"repost_share":0.034,"time_to_fill_p50_days":33,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":16500,"max_usd":46000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":23},"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-05-15T00:00:00Z","employer_posted_date":"2026-05-15","last_verified_at":"2026-10-17T08:22:10Z","board_verified":true,"closed_at":null,"days_open":155,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":155},"description":"We are looking for aSenior Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel.\nNVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!\nWhat you'll be doing:\nImplement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.\n\nLead the architecture and layout design of key memory subsystems, including control logic, sense amplifiers, I/O blocks, bit-cell arrays, and decoders for advanced technology nodes.\n\nDirect custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.\n\nBe responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.\n\nDrive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.\n\nProvide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.\n\nPossess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.\n\nDevelopment of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.\n\nCultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.\n\nExcel in resource management, representing the team in technical discussions with customers\n\nWhat we need to see:\nB.E/B Tech. / M Tech in Electronics or equivalent experience with 6+ Years of proven experience in Memory layout in advanced CMOS process.\n\nDetailed knowledge of industry standard EDA tools for Cadence.\n\nExperience with layout of high-performance memories of various types.\n\nKnowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)\n\nExperience with floor planning, block level routing and macro level assembly.\n\nDetailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.\n\nWe are an equal opportunity employer and value diversity at our company. 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