{"id":2767019,"url":"https://alion.io/job/nvidia-senior-mixed-signal-design-engineer-6","title":"Senior Mixed-Signal Design Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":792,"ghost_share":0.025,"stale_share":0.712,"repost_share":0.042,"time_to_fill_p50_days":33,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":136000,"max":218500,"currency":"USD","period":"year","gross":null,"usd_annual":218500},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Synopsys FineSim","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-03-10T00:00:00Z","employer_posted_date":"2026-03-10","last_verified_at":"2026-10-22T01:58:48Z","board_verified":true,"closed_at":null,"days_open":226,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":225},"description":"We are looking for an Engineer to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence!\nWe have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the high-speed Serdes platform for the future of computing. Join our dynamic team today!\nWhat you'll be doing:\nAs a key member of our circuit verification team, you will verify the design and implementation of the industry's leading GPU\n\nBe responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies\n\nUnderstand sophisticated mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design\n\nYou'll closely with multi-functional teams, circuit and logic design, verification, test engineering to accomplish tasks\n\nWhat we need to see:\nBachelors Degree in EE, CS or CE (or equivalent experience)\n\n5+ years of proven experience\n\nExperience in deep sub-micron process design experience in CMOS Analog / Mixed Signal Circuit Design\n\nSkilled using design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)\n\nExperience in crafting test bench environments for component and top level circuit verification\n\nExpertise in System Verilog or similar HVL\n\nHave strong debugging and analytical skills\n\nPerl and C/C++ programming language experience desirable\n\nStrong interpersonal skills and ability & desire to work as a great teammate are huge plus\n\nYour base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.You will also be eligible for equity and benefits.\nApplications for this job will be accepted at least until March 14, 2026.This posting is for an existing vacancy.\nNVIDIA uses AI tools in its recruiting processes.\nNVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.","description_format":"text","description_chars":2765,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-17T04:27:35Z"}],"visa":[],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":1,"p_active":0.223,"p_room":0.28,"age_days":225,"expected_fill_days":33,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":{"stated_usd_annual":218500,"is_top_pay":true},"html_url":"https://alion.io/job/nvidia-senior-mixed-signal-design-engineer-6","json_url":"https://alion.io/job/nvidia-senior-mixed-signal-design-engineer-6.json","meta":{"generated_at":"2026-10-22T02:24:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1868,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":6},"rest":"https://alion.io/mcp/rest/get_company?id=6"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnvidia-senior-mixed-signal-design-engineer-6"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnvidia-senior-mixed-signal-design-engineer-6"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnvidia-senior-mixed-signal-design-engineer-6"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nvidia-senior-mixed-signal-design-engineer-6\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnvidia-senior-mixed-signal-design-engineer-6"}]}