{"id":2779210,"url":"https://alion.io/job/nvidia-senior-physical-design-backend-engineer-2","title":"Senior Physical Design Backend Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":592,"ghost_share":0.019,"stale_share":0.66,"repost_share":0.034,"time_to_fill_p50_days":33,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Backend","role_family":"Backend","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Yokneam, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":95000,"max_usd":281000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":6933},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2025-11-06T00:00:00Z","employer_posted_date":"2025-11-06","last_verified_at":"2026-10-17T18:25:33Z","board_verified":true,"closed_at":null,"days_open":345,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":345},"description":"NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.\nWhat you'll be doing:\nPhysical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.\n\nBe exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.\n\nDaily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.\n\nTaking part in flows development.\n\nWhat we need to see:\nB.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.\n\n5+ years of experience in Physical Design.\n\nProven experience in RTL2GDS flows and methodologies.\n\nKnowledge in physical design flows and methodologies (PNR, STA, physical verification).\n\nDeep understanding of all aspects of Physical construction and Integration.\n\nStrong background of Physical Design Verification methodology LVS/DRC.\n\nFamiliarity with physical design EDA tools (such as Synopsys, Cadence, etc).\n\nGreat teammate.\n\nNVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? 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