{"id":35328,"url":"https://alion.io/job/nvidia-senior-soc-clocks-rtl-design-engineer","title":"Senior SOC Clocks RTL Design Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":765,"ghost_share":0.022,"stale_share":0.583,"repost_share":0.039,"time_to_fill_p50_days":40,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel","Yokneam, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":131000,"max_usd":300000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-01T00:00:00Z","employer_posted_date":"2026-08-01","last_verified_at":"2026-11-02T09:39:48Z","board_verified":true,"closed_at":null,"days_open":93,"trust":{"level":"ok","repost_count":1,"flags":[],"days_open":93},"description":"The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a Senior RTL Design Engineer to serve as the technical lead for clocks development on our next-generation networking chips. Clocks are the backbone of the SOC. In this role you will lead the development of the chip's clocking logic - PLL and reference clock integration, clock generation, distribution, muxing and dividers, glitchless switching, clock gating, reset synchronization, and the clock domain crossing infrastructure that every unit on the die depends on.\nThis is an RTL design and technical leadership role, not a circuit or transistor-level design role. Working from the clock architecture defined with the architecture and micro-architecture teams, you will lead its implementation in RTL, guide other engineers contributing to it, and drive it through to silicon in close partnership with Design Verification and Physical Design (backend). You will also interact regularly with CAD, Package Design, Software, and DFT teams.\nWhat you'll be doing:\nActing as the technical lead for SOC clocks development - leading the implementation of the clocking logic from specification through tape-out and bring-up\n\nWorking with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design\n\nWriting and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization\n\nLeading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team\n\nWorking hand-in-hand with the Physical Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence\n\nPartnering with Design Verification on clocking testplans, functional and gate-level debug, and coverage closure\n\nSupporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows\n\nRepresenting clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders\n\nWhat we need to see:\nB.Sc./M.Sc. in Electrical Engineering or Computer Engineering\n\n8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out\n\nDemonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams\n\nExpert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power\n\nDeep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing\n\nProficiency with design quality tooling - lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) - including the ability to interpret results and drive fixes back into the RTL\n\nExperience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up\n\nGreat teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams\n\nWays to stand out from the crowd:\nPrior hands-on experience with SOC-level clocking or reset logic on a taped-out chip\n\nExperience with PLL/clock generator integration and clock tree constraint development with backend teams\n\nExperience with high-speed networking, interconnect, or fabric designs\n\nBackground with low-power design techniques (clock gating, DVFS, power domains, UPF)\n\nExperience building automation for RTL integration, chip assembly, or design quality flows\n\nAt NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world.\nNVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.","description_format":"text","description_chars":4760,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Servers & Data Center Hardware","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-08-01T00:00:00Z"},{"event":"close","at":"2026-08-03T12:14:41Z"},{"event":"reopen","at":"2026-09-03T08:23:34Z"}],"visa":[],"liveness":{"score":14,"band":"cold","label":"Long shot","p_open":1,"p_active":0.503,"p_room":0.28,"age_days":93,"expected_fill_days":40,"reasons":["conf:7","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":null,"html_url":"https://alion.io/job/nvidia-senior-soc-clocks-rtl-design-engineer","json_url":"https://alion.io/job/nvidia-senior-soc-clocks-rtl-design-engineer.json","meta":{"generated_at":"2026-11-02T13:15:57Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18010,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-03T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":6},"rest":"https://alion.io/mcp/rest/get_company?id=6"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnvidia-senior-soc-clocks-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnvidia-senior-soc-clocks-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnvidia-senior-soc-clocks-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nvidia-senior-soc-clocks-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnvidia-senior-soc-clocks-rtl-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":35328}},{"tool":"search_jobs","arguments":{"company":"nvidia.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":35328},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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