{"id":3611862,"url":"https://alion.io/job/nvidia-senior-sta-engineer","title":"Senior STA Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":792,"ghost_share":0.023,"stale_share":0.573,"repost_share":0.044,"time_to_fill_p50_days":40,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Tel Aviv, Israel"],"countries":["IL"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-11-02T14:38:51Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-04T08:16:23Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels.\nWhat you’ll be doing:\nDrive static timing analysis and timing closure for block and/or full-chip designs.\nDevelop, review, and debug timing constraints, scenarios, and signoff checks.\nAnalyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams.\nPartner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities.\nReview reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact.\nImprove timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python.\nWhat we need to see:\nB.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.\n5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation.\nStrong understanding of static timing analysis fundamentals, timing constraints, and timing closure.\nHands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalent.\nExperience debugging setup/hold violations, clocking issues, and ECO impacts.\nSolid scripting skills in Tcl plus familiarity with Perl or Python.\nGood communication skills and ability to work across design, CAD, and verification teams.\nWays to stand out from the crowd:\nExperience with advanced-node implementation and signoff.\nKnowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis.\nExperience improving timing methodology or developing reusable automation.\nWe are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided a reasonable accommodation to participate in the job application or interview process, perform essential job functions, and receive other benefits and privileges of employment. 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