{"id":2736179,"url":"https://alion.io/job/nvidia-signal-and-power-integrity-engineer","title":"Signal and Power Integrity Engineer","company":{"id":6,"name":"NVIDIA","domain":"nvidia.com","url":"https://alion.io/company/nvidia","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":778,"ghost_share":0.026,"stale_share":0.725,"repost_share":0.041,"time_to_fill_p50_days":33,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shenzhen, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":66000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":5425},"experience_years_min":1,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Allegro","optional":false},{"name":"Cadence Sigrity","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HSPICE","optional":false}],"status":"live","first_seen_at":"2026-05-13T00:00:00Z","employer_posted_date":"2026-05-13","last_verified_at":"2026-10-20T20:08:30Z","board_verified":true,"closed_at":null,"days_open":161,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":160},"description":"We are now looking for Signal & Power Integrity Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. This is a dynamic team working with state of the art, unique technology. If you are someone that loves a challenge, come join this diverse team and help move the needle!\nWhat you'll be doing:\nDrive board/system level signal and power integrity requirements\n\nLead board/system SI/PI design activities, including PCB stackup/material selection, design guide implementation, layout review, and post-layout analysis\n\nWork closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis\n\nDevelop novel algorithms & new methodologies to improve SI/PI modeling efforts\n\nWork with Application Engineering teams to support customers w/ SI/PI questions\n\nVNA & TDR measurements to support model correlation efforts and improve confidence in design stage\n\nWhat we need to see:\nMS/BS in EE or equivalent experience\n\nMinimum 1+ years of experience as a SI/PI engineer\n\nDeep understanding of electromagnetic, specifically electromagnetic waves including transmission line theory and via properties\n\nProficient with HFSS, Sigrity, Hspice, and/or other simulation tools\n\nExperienced with Cadence Allegro PCB designer and Constraints Manager\n\nUnderstanding of high volume manufacturing variations and impact to channel signal integrity\n\nExposure to lab measurements including VNA & TDR experience\n\nPassionate about SI/PI work\n\nGood written & verbal interpersonal skills in English\n\nWays to stand out from the crowd:\nFamiliarity with NRZ/PAM-4 signaling schemes\n\nExposure to interface timing budgets and system modeling\n\nFamiliarity with high-speed I/O design concepts including clock generation, transmitter & receiver design, and equalization schemes\n\nPDN analyses including model generation and time domain simulation\n\nExperience w/ Matlab, Python, and C as well as exposure to package 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