{"id":103866,"url":"https://alion.io/job/nxp-digital-verification-engineer-4","title":"Digital Verification Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":175,"ghost_share":0,"stale_share":0.623,"repost_share":0,"time_to_fill_p50_days":43,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Glasgow, United Kingdom"],"countries":["GB"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":59000,"max_usd":115000,"period":"year","method":"role_country_seniority_unknown","sample_n":105},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-07-24T00:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-10-25T11:50:29Z","board_verified":true,"closed_at":null,"days_open":93,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":93},"description":"We are actively expanding the Crypto & Security Competence Centre (CCC&S) at NXP and we have new opportunities in our team for digital verification engineers working on next-generation security technologies such as:\nPost-Quantum Cryptography (PQC) IP\nSecure SoC subsystems, including next-generation roots of trust\nHigh-assurance cryptographic accelerators for future platforms\nAt CCC&S, we are also driving a significant transformation in how hardware is designed and verified by integrating AI directly into IC design and verification flows. The role is blended with traditional verification methods whilst the AI agents are being developed. The role is blended with traditional verification methods whilst the AI agents are being developed.\nDriven Verification - What You’ll Be Part Of\nIn this role, you will contribute to a step-change in verification capability through:\nAI-driven verification automation - reducing regression effort while maintaining full coverage\nIntelligent debug and analysis - accelerating bug discovery and root-cause identification\nAutomated test and vPlan generation - improving consistency and reducing human error\nWe are also actively developing advanced capabilities including:\nAI-assisted RTL understanding and test explanation\nConversational debug interfaces for waveform and design interaction\nAI-driven coverage closure and test prioritisation\nThis is not a future vision-this transformation is already underway within CCC&S workflows.\nWhy This Role Stands Out\nWork on cutting-edge cryptography technologies critical to future cybersecurity\nHelp define how AI transforms verification workflows and methodologies\nJoin a growing organisation where your input shapes tools, processes, and technical direction\nTake ownership of high-visibility, complex projects from concept to silicon\nYour Responsibilities\nVerification of digital hardware architectures.\nCreating, reviewing, and maintaining verification plans, and tracking verification progress.\nSpecifying and developing verification strategies, tests, and environments for security features and hardware co-processors.\nWorking with emerging verification methodologies and introducing them into existing verification flows.\nYour Profile\nBSc., or MSc., degree in Electronics or Electrical Engineering. \nSome experience with SystemVerilog for testbench development and verification.\nSome experience in UVM (Universal Verification Methodology), including component creation, sequences, drivers, monitors, and scoreboards.\nSolid understanding and practical use of Constrained Random Verification techniques.\nExperience with Metrics-Driven Verification, including functional coverage and verification planning.\nAbility to write SystemVerilog Assertions (SVA) for protocol and design checking.\nDemonstrated success in achieving Coverage Closure across functional and code coverage metrics.\nExperience analysing coverage results and refining test strategies to close gaps.\nStrong debugging skills across simulations and complex verification environments.\nKnowledge of Formal Verification methods would be advantageous.\nMore information about NXP in the United Kingdom...\n#LI-c856","description_format":"text","description_chars":3159,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless 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