{"id":103777,"url":"https://alion.io/job/nxp-principal-digital-design-engineer","title":"Principal Digital Design Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":200,"ghost_share":0,"stale_share":0.92,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-08-21T00:00:00Z","employer_posted_date":"2026-08-21","last_verified_at":"2026-10-18T07:33:41Z","board_verified":true,"closed_at":null,"days_open":58,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":58},"description":"An experienced Digital Design Engineer is responsible for designing, developing, and optimizing digital logic circuits and systems for semiconductor, FPGA, or ASIC-based products. The role involves working across the full design cycle-from specification and RTL design to verification, synthesis, and silicon validation.\nKey Responsibilities\nDesign and develop RTL (Register Transfer Level) code using Verilog/SystemVerilog/VHDL\nArchitect and implement complex digital blocks and subsystems\nPerform functional verification using simulation tools and methodologies (UVM/OVM)\nDevelop and execute testbenches and validation plans\nPerform logic synthesis, timing analysis, and area optimization\nDebug and troubleshoot design issues at RTL, gate, and silicon levels\nCollaborate with verification, physical design, and firmware teams\nEnsure designs meet power, performance, and area (PPA) targets\nParticipate in design reviews, code reviews, and technical discussions\nWork with EDA tools for design implementation and validation\nSupport post-silicon validation and bring-up activities\nRequired Skills & Expertise\nTechnical Skills\nStrong proficiency in:Verilog / SystemVerilog / VHDL\n\nExperience with:RTL design and simulation tools (ModelSim, VCS, Xcelium)\nSynthesis tools (Design Compiler, Genus)\nStatic Timing Analysis (PrimeTime)\n\nUnderstanding of:Digital logic design concepts\nFSMs, pipelining, clock domain crossing (CDC)\nLow-power design techniques\n\nKnowledge of:FPGA/ASIC design flow\nBus protocols (AXI, AHB, APB)\n\nExperience in debugging using:Waveform tools (Verdi, SimVision)\n\nPreferred Skills\nExperience with UVM-based verification methodology\nFamiliarity with DFT (Design for Testability) concepts\nExposure to scripting languages like Python, Perl, or TCL\nKnowledge of hardware-software co-design\nExperience in high-speed interfaces or SoC design\nExperience Requirements\nTypically 10+ years of experience in digital design or ASIC/FPGA development\nProven track record of successful tape-outs or product deliveries\nEducation\nBachelor’s or Master’s degree in:Electronics Engineering\nElectrical Engineering\nVLSI Design\nComputer Engineering\n\nSoft Skills\nStrong problem-solving and debugging abilities\nExcellent communication and teamwork skills\nAbility to work in fast-paced, deadline-driven environments\nAttention to detail and quality-focused mindset\n More information about NXP in India...\n#LI-29f4","description_format":"text","description_chars":2403,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-08-21T00:00:00Z"}],"visa":[],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":1,"p_active":0.466,"p_room":0.45,"age_days":57,"expected_fill_days":34,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":null,"html_url":"https://alion.io/job/nxp-principal-digital-design-engineer","json_url":"https://alion.io/job/nxp-principal-digital-design-engineer.json","meta":{"generated_at":"2026-10-18T11:29:14Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17001,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-19T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":17368},"rest":"https://alion.io/mcp/rest/get_company?id=17368"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnxp-principal-digital-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnxp-principal-digital-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnxp-principal-digital-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nxp-principal-digital-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnxp-principal-digital-design-engineer"}]}