{"id":106884,"url":"https://alion.io/job/nxp-principal-hardware-asic-architect-engineer","title":"Principal Hardware ASIC Architect engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":174,"ghost_share":0,"stale_share":0.632,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":62000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Quantization","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-07-16T00:00:00Z","employer_posted_date":"2026-07-16","last_verified_at":"2026-10-29T02:44:16Z","board_verified":true,"closed_at":null,"days_open":105,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":105},"description":"Job Description\nJob Title: Principal Hardware ASIC Architect Engineer\nHyderabad, India\nAbout the Role\nWe are seeking an experienced Hardware Architect with strong expertise in SOC-architecture, Micro-architecture design, RTL coding and system-level performance/power analysis.\nThe ideal candidate will have a track record of owning complex blocks or subsystems from concept through silicon, balancing performance, power, and area (PPA), and working closely with software, asic-design, asic-verification, asic-physicaldesign teams. it requires deep architectural insight and hands-on implementation understanding to help guide design trade-offs and drive the next generation of AI inference accelerators.\nThis is what you are responsible for\nArchitecture & Micro-Architecture\nDefine product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip.\nCollaborate with various software teams to co-optimize hardware features for AI workloads.\nCollaborate with RTL designers to identify complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals\nCollaborate with Physical-design teams for Area/Floorplan refinement, Timing targets etc.\nDefine and document interface specifications, control/status logic, and pipeline structures.\nLead PPA analysis and trade-off discussions across RTL and architecture.\nAI Workloads & HW-SW Co-Design\nCollaborate closely with various software to co-optimize hardware features for real-world AI inference workloads.\nIncorporate considerations such as, quantization, sparsity, dataflow, scheduling, memory bandwidth into architectural decisions.\nGuide hardware features that improve programmability, debuggability, and long-term software scalability.\nModelling & Analysis\nDevelop and maintain high-level architecture and performance models.\nUse simulation and architectural models to guide RTL-level improvements.\nValidate model predictions against RTL or emulation results and refine accordingly.\nStrong understanding of AI inference workloads, dataflows, quantization, and memory/bandwidth bottlenecks in edge deployments\nNecessary Qualifications:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.\n12+ years of experience in SOC design, SOC architecture, RTL design, micro-architecture.\nStrong understanding of computer architecture, memory hierarchies, SoC interconnects, and AI/ML compute architectures.\nProven experience optimizing for performance, power, and area.\nHands-on expertise in Verilog/SystemVerilog, C/C++, and scripting (Python/Tcl/Perl)\nPreferred Qualifications:\nExperience with AI accelerators, DSPs, or high-performance CPUs/GPUs.\nFamiliarity with performance modeling frameworks (e.g., Python/C++ based).\nExposure to EDA tools, power/performance analysis, and hardware-software co-design.\nStrong analytical skills and a collaborative mindset.\n More information about NXP in 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