{"id":2897414,"url":"https://alion.io/job/nxp-semiconductors-lead-dft-engineer-2","title":"Lead DFT Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":182,"ghost_share":0,"stale_share":0.632,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":46000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-06-29T00:00:00Z","employer_posted_date":"2026-06-29","last_verified_at":"2026-10-22T03:22:24Z","board_verified":true,"closed_at":null,"days_open":115,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":115},"description":"Summary: We are looking for an experienced and highly motivated DFT Lead Engineer with strong expertise in Design-for-Test methodologies for complex SoC/ASIC designs. The ideal candidate should have hands-on experience in Scan Insertion, ATPG, MBIST, LBIST, JTAG, Silicon Bring-up & Debug, and should be capable of driving complete DFT implementation and signoff activities from RTL to silicon validation.\nThe candidate will work closely with Design, Physical Design, Verification, and Post-Silicon teams to ensure high test coverage, manufacturability, and robust silicon quality.\nJob Qualifications\nB.Tech / M.Tech in Electronics, Electrical, or related field\n5-8 years of experience in core DFT\nStrong expertise in ATPG and LBIST methodologies\nSolid hands-on experience in scan insertion and compression\nStrong understanding and hands-on experience with iJTAG (IEEE 1687)\nExperience in MBIST architectures and repair flows\nGood understanding of Boundary Scan / JTAG and related standards (1149.1, 1500, 1687 preferred)\nExposure to low-power DFT concepts\nExperience in testability analysis and silicon debug\nStrong problem-solving and debugging skills\nAbility to work in a cross-functional team environment\nGood communication and mentoring skills\nJob Responsibilities\nLead end-to-end DFT implementation for SoC subsystems\nDrive DFT RTL integration and verification activities\nManage cross-functional coordination for DFT deliverables at block/subsystem level\nImplement full-scan DFT methodologies\nDevelop and optimize scan insertion and compression techniques\nExecute ATPG flows to achieve required fault coverage\nDefine and implement MBIST architectures, including repair flows\nSupport LBIST planning and implementation\nImplement and ensure compliance with Boundary Scan / JTAG requirements\nApply low-power DFT methodologies\nPerform testability analysis and improve design coverage\nSupport silicon debug and failure analysis\n More information about NXP in India...\n#LI-7013","description_format":"text","description_chars":1976,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-20T05:18:27Z"}],"visa":[],"liveness":{"score":12,"band":"cold","label":"Long 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