{"id":1174316,"url":"https://alion.io/job/nxp-semiconductors-lead-pdn-emir-engineer","title":"Lead PDN EMIR Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":168,"ghost_share":0,"stale_share":0.685,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":23000,"max_usd":58000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"ANSYS","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-09-24T10:32:36Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-11-04T16:40:34Z","board_verified":true,"closed_at":null,"days_open":41,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":41},"description":"Required Qualifications\nB.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related field.\n8+ years of experience in Physical Design, Power Integrity, or Signoff.\nKey Responsibilities\nTechnical Skills:\nOwn full-chip and subsystem-level PDN signoff for complex SoCs.\nDefine PDN signoff criteria across project milestones.\nDrive power integrity closure for functional, DFT, LBIST, capture, and stress modes.\nLead package-aware IR/EM analysis and chip-package co-optimization.\nDefine and review power grid architecture, bump planning, power switch strategy, and decap methodology.\nDrive Vmin, peak EM, dynamic IR, and thermal-aware analysis.\nMethodology & Innovation\nDevelop next-generation PDN signoff methodologies.\nAutomate PDN flows using TCL/Python/Shell.\nImprove runtime, capacity, dashboarding, and regression infrastructure.\nCollaborate with EDA vendors (Ansys/Cadence/Synopsys) for feature enhancements and tool debug.\nEstablish best practices and reusable signoff frameworks across projects.\nCross-Functional Collaboration\nWork closely with Physical Design teams to drive PDN-aware floorplanning, placement, routing, and ECO solutions.\nPartner with DFT teams to optimize pattern power and capture-mode reliability.\nCollaborate with Package and Thermal teams on package RLC optimization and thermal correlation.\nSupport silicon bring-up, debug, and correlation of pre-silicon versus post-silicon measurements.\nProject Execution\nProvide technical risk assessment and mitigation plans.\nDrive closure of critical PDN hotspots with minimal PPA impact.\nPresent signoff status to management and project stakeholders.\nEnsure on-time delivery for tapeout milestones.\nLead reviews for high-risk blocks and top-level integrations.\nPeople Leadership\nMentor engineers and PDN owners across multiple projects.\nDefine training content and technical roadmaps for the team.\nLead technical reviews and establish signoff governance.\nInfluence organizational PDN strategy and future technology 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