{"id":1438181,"url":"https://alion.io/job/nxp-semiconductors-packaging-development-engineer","title":"Packaging development engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":78,"open_postings":125,"ghost_share":0,"stale_share":0.888,"repost_share":0,"time_to_fill_p50_days":38,"computed_at":"2026-10-02T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Kuala Lumpur, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17000,"max_usd":38000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":3947},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-09-29T04:06:47Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-02T16:32:08Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"The Senior Flip-Chip Front-End Packaging Development Engineer - Die Attach & Underfill is responsible for leading FC-FE process development, optimization, and integration activities for die attach and underfill process. This role requires strong technical capability in process characterization, DOE, troubleshooting, yield improvement, material qualification, and equipment readiness to support packages development and production release. The engineer will work closely with cross-functional teams to ensure robust process performance, manufacturability, reliability, and continuous improvement across flip-chip packaging platforms.\nProcess Ownership & Optimization\nTake ownership of FC-FE die attach and underfill processes for semiconductor packages, including advanced package platforms.\nDefine, develop, optimize, and maintain critical process parameters for die placement, bonding, reflow, underfill dispensing, cure, CSAM, and related process controls.\nLead design of experiments (DOE) activities to improve process yield, product reliability, void control, fillet quality, underfill flow, curing profile, and CSAM performance.\nDiagnose and resolve complex front-end process defects through systematic analysis and data-driven decision-making.\nAdvanced Troubleshooting & Yield Improvement\nDrive root cause analysis for yield excursions using structured problem-solving methodologies, including 8D, Fishbone, 5-Why, and FTA.\nDevelop and implement corrective and preventive actions to sustain yield improvement and prevent recurrence.\nMonitor yield performance and initiate continuous improvement projects to enhance process capability.\nAnalyze inline process data and reliability results to identify potential process risks and improvement opportunities.\nTooling & Equipment Management\nLead tooling, fixture, and dispense process improvements in collaboration with vendors to support first-time NPI-development requirements.\nSupport die attach and underfill, CSAM equipment qualification, calibration, upgrades, and readiness for production deployment.\nNew Product Leadership\nLead process development activities for new packages from concept phase through production release.\nConduct technology research, process characterization, and process window development to support NPI readiness.\nCollaborate with the design engineering team to define and validate Design for Manufacturability (DFM) requirements.\nPrepare and maintain process documentation, including specifications, work instructions, control plans, and related technical records. \nMaterial & Process Integration\nEvaluate and qualify FC-FE-related materials, including die attach materials, flux, underfill, and associated consumables to support process performance, manufacturability, and reliability requirements.\nWork closely with supplies to address material-related issues, drive improvements, and support qualification activities.\nAccess interactions among die attach process design, underfill material properties, curing conditions, CSAM results, package structure, and reliability performance to ensure robust process integration.\nEstablish underfill inspection and acceptance criteria, including CSAM verification for voids, delamination, non-wet, flow coverage, and cure-related defects.\nExperience or familiarity with AI-based simulation tools will be considered an advantage. \nCross-Functional & Leadership Role\nServe as the technical lead across operations, quality, product engineering, suppliers, and subcontractors to ensure process alignment and performance.\nMentor junior engineers and technicians in process development, equipment troubleshooting, and structured problem-solving.\nProvide proactive technical support for failure analysis reviews, risk assessments, and cross-functional technical discussions.\nQualifications Education\nBachelor’s degree in Mechanical Engineering, Materials Science, Chemical Engineering, or a related discipline.\nExperience\nMinimum of five years of experience in semiconductor packaging, with strong exposure to FC-FE die attach, and underfill dispensing processes. Familiarity with the end-to-end flip-chip process flow will be considered an advantage.\nDemonstrated hands-on experience in high-volume manufacturing and fast-paced development environments.\n More information about NXP in Malaysia...\n#LI-633a","description_format":"text","description_chars":4324,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Science & Engineering","Electrical & Electronic Engineering","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-29T04:06:47Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":3,"expected_fill_days":38,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-02T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/nxp-semiconductors-packaging-development-engineer","json_url":"https://alion.io/job/nxp-semiconductors-packaging-development-engineer.json","meta":{"generated_at":"2026-10-03T04:19:21Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4498,"day_limit":5000,"remaining_today":502,"minute_limit":60,"resets_at":"2026-10-04T00:00:00Z"}}}