{"id":3424583,"url":"https://alion.io/job/nxp-semiconductors-physical-design-lead","title":"Physical Design Lead","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":174,"ghost_share":0,"stale_share":0.632,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":71000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Innovus","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"TCL Scripting","optional":false}],"status":"live","first_seen_at":"2026-10-28T21:57:32Z","employer_posted_date":"2026-10-28","last_verified_at":"2026-10-30T05:09:35Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"As a Physical Design Lead Engineer, you will serve as a key technical leader responsible for the end-to-end physical implementation of complex SoCs and IPs on advanced technology nodes. You will own large and challenging design partitions or drive critical top-level physical design activities, including floorplanning, place-and-route, timing closure, and signoff.\nYou will play a pivotal role in achieving ambitious power, performance, area (PPA), quality, and schedule goals while providing technical leadership, mentoring engineers, and driving methodology improvements across multiple projects.\nKey Responsibilities\nLead and execute all aspects of physical design from RTL to GDSII, including synthesis, floorplanning, power planning, place and route, clock tree synthesis (CTS), timing closure, physical verification, and tapeout.\nOwn the complete physical implementation of complex SoC partitions, subsystems, or top-level designs and drive closure to production-quality signoff.\nPerform and drive advanced static timing analysis (STA), multi-corner multi-mode (MCMM) optimization, timing ECO implementation, and signoff closure.\nDrive closure across power, performance, area, signal integrity (SI), electromigration (EM), IR-drop, reliability, and manufacturability targets.\nDevelop and optimize physical design methodologies, automation frameworks, flows, and scripts to improve design quality, efficiency, and turnaround time.\nAnalyze critical timing paths, congestion, routing, and power bottlenecks, and develop innovative solutions to achieve aggressive PPA goals.\nCollaborate closely with architecture, RTL design, verification, DFT, package, and technology teams to resolve implementation challenges and optimize overall product quality.\nDrive physical signoff activities including DRC, LVS, antenna checks, density closure, metal fill verification, and tapeout readiness reviews.\nContribute to architecture and design reviews by providing implementation-driven feedback to improve PPA and physical feasibility.\nEvaluate and deploy new EDA tools, methodologies, and advanced implementation techniques.\nImplement advanced low-power design methodologies including clock gating, power gating, multi-voltage design, retention, isolation, and UPF/CPF-based flows.\nMentor and guide engineers, providing technical leadership and fostering engineering excellence across teams.\nGenerate comprehensive implementation reports, signoff documentation, and design reviews throughout the development cycle.\nRequired Qualifications\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.\n15+ years of ASIC/SoC physical design experience with a proven record of successful tapeouts on advanced process technologies.\nExtensive hands-on experience in synthesis, floorplanning, place and route, timing analysis, physical verification, and signoff closure.\nProven ability to independently drive block-level, subsystem-level, and top-level implementation of complex multi-million gate SoCs, including multi-processor architectures.\nStrong expertise in one or more of the following domains: Physical Design & Implementation Synthesis & Timing Analysis\nDeep understanding of MCMM timing closure methodologies, timing constraint development, ECO implementation, and signoff flows.\nHands-on experience with industry-standard EDA tools, including: Cadence Innovus and Tempus Synopsys Fusion Compiler, ICC2, and PrimeTime Ansys RedHawk or equivalent EM/IR analysis tools\nStrong knowledge of physical signoff methodologies including DRC, LVS, antenna checks, density validation, and metal fill closure.\nExperience with signal integrity analysis, crosstalk mitigation, electromigration (EM), and IR-drop closure.\nStrong understanding of manufacturability requirements and Design for Manufacturability (DFM) principles.\nProficiency in Tcl scripting and working knowledge of Python and/or Perl for automation, reporting, and flow development.\nDemonstrated ability to drive multiple implementation experiments and optimize designs against challenging PPA targets.\nExperience with advanced process nodes including 16nm FinFET and below; experience in 7nm, 5nm, or more advanced technologies is a plus.\nHands-on experience with low-power design techniques including clock gating, power gating, multi-voltage implementation, retention, isolation, and UPF/CPF methodologies.\nDemonstrated technical leadership, mentorship, and ability to drive cross-functional initiatives.\nExcellent problem-solving, analytical, debugging, communication, and stakeholder management skills.\nAbility to thrive in a fast-paced, collaborative, and globally distributed engineering environment.\nPreferred Qualifications\nExperience leading physical implementation and signoff for large-scale SoCs across multiple engineering sites.\nExperience developing organization-wide design methodologies, automation frameworks, and best practices.\nStrong understanding of advanced-node challenges including congestion management, variation-aware timing closure, power integrity, and reliability signoff.\nExperience evaluating and deploying next-generation EDA technologies and AI-assisted design optimization techniques.\n More information about NXP in India...\n#LI-9415","description_format":"text","description_chars":5281,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-28T21:57:32Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":44,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":null,"html_url":"https://alion.io/job/nxp-semiconductors-physical-design-lead","json_url":"https://alion.io/job/nxp-semiconductors-physical-design-lead.json","meta":{"generated_at":"2026-10-30T14:38:28Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2204,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":17368},"rest":"https://alion.io/mcp/rest/get_company?id=17368"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnxp-semiconductors-physical-design-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnxp-semiconductors-physical-design-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnxp-semiconductors-physical-design-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nxp-semiconductors-physical-design-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnxp-semiconductors-physical-design-lead"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3424583}},{"tool":"search_jobs","arguments":{"company":"nxp.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3424583},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}