{"id":1936265,"url":"https://alion.io/job/nxp-semiconductors-senior-analog-ic-layout-engineer-mcu","title":"Senior Analog IC Layout Engineer - MCU","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":175,"ghost_share":0,"stale_share":0.623,"repost_share":0,"time_to_fill_p50_days":43,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Catania, Italy"],"countries":["IT"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":58000,"max_usd":107000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":20},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false}],"status":"live","first_seen_at":"2026-10-05T23:41:52Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-25T11:50:29Z","board_verified":true,"closed_at":null,"days_open":20,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":20},"description":"Role Summary\nThe Senior Layout Engineer is a highly skilled technical contributor responsible for the physical implementation of complex analog, mixed-signal, and custom IC designs. Working with a high degree of independence, this role drives layout execution from floorplanning through tape-out, ensuring that performance, quality, reliability, and schedule objectives are achieved.\nThe position requires strong expertise in advanced layout methodologies, excellent problem-solving capabilities, and effective collaboration with design, verification, and technology teams. In addition to delivering critical project milestones, the engineer provides technical guidance to less experienced engineers, contributes to methodology improvements, and plays a key role in mitigating project risks and supporting successful silicon delivery.\nKey Responsibilities\nLead the layout implementation of complex analog, mixed-signal, and custom digital blocks.\nDrive floorplanning, device matching, routing strategies, and layout optimization to meet performance, area, power, reliability, and manufacturability requirements.\nPerform and review physical verification activities, including DRC, LVS, ERC, EM/IR, latch-up, density, and reliability checks.\nCollaborate closely with design, verification, technology, and product engineering teams to resolve layout-related challenges and achieve project milestones.\nSupport advanced-node technologies, including FinFET processes, and contribute to methodology improvements and best practices.\nProvide technical guidance and mentorship to junior engineers and contractors.\nAssess project risks, estimate layout effort, and drive execution to meet aggressive schedules.\nExpected Competencies\nStrong expertise in analog layout techniques, matching, shielding, noise isolation, ESD-aware layout, power distribution, and high-performance routing.\nExcellent understanding of semiconductor process technologies, including planar and FinFET nodes.\nProficiency with industry-standard EDA tools and physical verification flows.\nAbility to independently make technical trade-offs and solve complex implementation issues.\nStrong communication and stakeholder management skills.\nProven track record of successful tape-outs and delivery of high-quality silicon.\nImpact and Leadership\nRecognized technical expert within the layout organization.\nInfluences project execution and physical design methodologies across multiple programs.\nContributes to organizational capability growth through mentoring, reviews, and knowledge sharing.\nPlays a key role in achieving project schedules and silicon quality targets.\nQualifications\nBSEE or MSEE.\nApproximately 8-12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.\nExpert in Cadence Virtuoso XL, Floorplanning, Constraint Driven Layout, and PVS DRC/LVS/ERC.\nStrong knowledge of matching, common centroid, shielding, EM/IR, high-speed routing, parasitics, and DFM practices.\nProven experience leading analog-on-top and digital-on-top chip layouts.\nExperience with floorplanning, power distribution, ESD, and multiple voltage domains.\nFamiliarity with PLL, OSC, ADC, DAC, LDO, Bandgap, and high-speed interface circuits.\nExcellent communication and cross-functional leadership skills.\nFluent in English\nSKILL or Perl scripting is a plus.\n-----------\nNXP is committed to equal pay for equal work and work of equal value and applies fair, consistent and transparent remuneration practices.\nAs of the date of this posting, the estimated gross annual base salary range for this position in Italy is between 50,600 € and 69,600 € annually. This range is intended as a guideline. Actual compensation may vary based on qualifications, experience, skills, and specific business or organizational needs. This position falls under the applicable National Collective Labour Agreement (Metalmeccanica Industria). Where relevant, the total compensation package may also include additional elements such as annual incentive opportunities and/or equity, along with a competitive benefits package.More information about NXP in Italy...\n-----------\n#LI-7795","description_format":"text","description_chars":4128,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Science & Engineering","Electrical & Electronic Engineering","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-05T23:41:52Z"}],"visa":[],"liveness":{"score":55,"band":"ok","label":"Likely open","p_open":1,"p_active":0.616,"p_room":0.9,"age_days":19,"expected_fill_days":43,"reasons":["conf:0","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/nxp-semiconductors-senior-analog-ic-layout-engineer-mcu","json_url":"https://alion.io/job/nxp-semiconductors-senior-analog-ic-layout-engineer-mcu.json","meta":{"generated_at":"2026-10-26T01:31:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1968,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":17368},"rest":"https://alion.io/mcp/rest/get_company?id=17368"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnxp-semiconductors-senior-analog-ic-layout-engineer-mcu"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnxp-semiconductors-senior-analog-ic-layout-engineer-mcu"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnxp-semiconductors-senior-analog-ic-layout-engineer-mcu"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nxp-semiconductors-senior-analog-ic-layout-engineer-mcu\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnxp-semiconductors-senior-analog-ic-layout-engineer-mcu"}]}