{"id":2383384,"url":"https://alion.io/job/nxp-semiconductors-senior-analog-ic-layout-engineer","title":"Senior Analog IC Layout Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":178,"ghost_share":0,"stale_share":0.629,"repost_share":0,"time_to_fill_p50_days":43,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Guadalajara, Mexico"],"countries":["MX"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":52000,"max_usd":118000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Cadence Quantus","optional":true},{"name":"Python","optional":true},{"name":"Siemens Calibre","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-10-12T19:49:49Z","employer_posted_date":"2026-10-12","last_verified_at":"2026-10-27T05:59:25Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"About the Team\nNXP Semiconductors is seeking an experienced Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS).\nThe Central Layout Group delivers physical implementation expertise for complex mixed-signal and power management integrated circuits supporting multiple product lines worldwide. The team collaborates with Design, Verification, Package, Test and Product Engineering organizations across a global R&D network to drive the successful execution of advanced automotive and industrial semiconductor products.\nRole Summary\nThe successful candidate will play a key role in the development of complex automotive mixed-signal and power management ICs, driving layout execution from planning through tape-out while collaborating with stakeholders across multiple worldwide engineering sites.\nResponsibilities：\nLayout Execution\nLead the physical implementation of Analog and Mixed-Signal integrated circuits\nDefine and optimize floorplans for complex blocks and top-level assemblies\nDrive layout activities from planning through tape-out\nEnsure design quality, robustness and compliance with development methodologies\nVerification and Sign-Off\nOwn DRC, LVS, ERC and physical sign-off activities\nSupport extraction analysis and post-layout verification\nDrive root-cause analysis and resolution of layout-related challenges\nTechnical Leadership\nCoordinate layout activities with Design, Verification, Package, Test and Product Engineering teams\nMentor junior engineers and share technical expertise\nContribute to layout methodology improvements and best practices\nSupport project execution through accurate planning, communication and risk management\nRequirements:\nBachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics\nStrong experience in Analog IC Layout development\nExpertise with Cadence Virtuoso Layout environment\nExperience with DRC/LVS sign-off methodologies\nSolid understanding of CMOS, BCD, SOI and Mixed-Signal design environments\nAbility to work independently and manage complex technical challenges\nStrong communication, collaboration and stakeholder management skills\nFluent written and spoken English\nPreferred Qualifications\nExperience with Calibre, PVS, Quantus, StarRC or equivalent EDA tools\nExperience with automotive semiconductor products\nKnowledge of High Voltage technologies\nExperience in layout automation and scripting (SKILL, Python, TCL or Shell)\nPrevious mentoring or technical leadership experience\nExperience working in multi-site international R&D organizations\nInterest in AI-assisted engineering and design productivity solutions\n More information about NXP in Mexico...\n#LI-fcc3","description_format":"text","description_chars":2760,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power 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