{"id":158931,"url":"https://alion.io/job/nxp-semiconductors-senior-digital-design-engineer","title":"Senior Digital Design Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":178,"ghost_share":0,"stale_share":0.629,"repost_share":0,"time_to_fill_p50_days":43,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Pune, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":50000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys Formality","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-08-27T00:00:00Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-10-28T00:50:29Z","board_verified":true,"closed_at":null,"days_open":62,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":62},"description":"Job Position : Synthesis & Front-End Implementation Engineer\nJob Description\nWe are seeking a highly motivated Synthesis & Front-End Implementation Engineer to join our dynamic team. In this role, you will be crucial in translating RTL designs into optimized gate-level netlists, ensuring performance, power, and area targets are met for complex IP blocks.\nJob Responsibilities\nAs a Synthesis & Front-End Implementation Engineer, your responsibilities will include:\n* Performing synthesis of RTL designs for various digital blocks and sub-systems, including hierarchical synthesis methodologies.\n* Developing and implementing robust timing constraints (SDC) to achieve target frequencies and optimize design performance.\n* Conducting STA, identifying critical paths, and collaborating with design teams for timing closure.\n* Executing formal verification (LEC) to ensure functional equivalency between RTL and synthesized netlists.\n* Analyzing and optimizing power consumption at the front-end stage, utilizing power analysis tools and techniques.\n* Performing area estimation and optimization to meet aggressive chip size requirements.\n* Collaborating closely with RTL designers, DFT engineers, and physical design engineers to ensure seamless integration and hand-off.\n* Developing and maintaining automation scripts (Tcl, Python, Perl) for synthesis flows and design analysis.\n* Evaluating and integrating new CAD tools and methodologies to improve efficiency and design quality.\n* Documenting design constraints, methodologies, and analysis results thoroughly.\nJob Qualifications\nTo be successful in this role, you should possess the following qualifications:\n* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\n* 5+ years of relevant experience in digital ASIC/SoC design, with a focus on synthesis and front-end implementation.\n* Proficiency with industry-standard synthesis tools (e.g., Synopsys Design Compiler, Synopsys Fusion Compiler or similar).\n* Strong understanding of static timing analysis (STA) concepts and tool (e.g., Synopsys PrimeTime).\n* Experience with formal verification tools (e.g., Synopsys Formality, Cadence Conformal (LEC)).\n* Understanding of upf, low-power design techniques and power analysis concepts.\n* Solid knowledge of Verilog/System verilog for digital design.\n* Familiarity with scripting languages (Tcl, Python, Perl) for automation.\n* Knowledge of DFT (Design for Testability) principles is a plus.\n* Excellent problem-solving skills and attention to detail.\n* Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment across multiple time zones.\n More information about NXP in India...\n#LI-2734","description_format":"text","description_chars":2749,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power 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