{"id":2897386,"url":"https://alion.io/job/nxp-semiconductors-senior-ip-design-engineer","title":"Senior IP Design Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":84,"open_postings":182,"ghost_share":0,"stale_share":0.637,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":52000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-09-29T00:00:00Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-22T03:22:24Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"In this role, you will be responsible for developing high-quality, reusable IPs for SoC/subsystem integration and driving designs from concept through silicon. This position offers an opportunity to work on cutting-edge semiconductor technologies and collaborate with global cross-functional teams.\nKey responsibilities\nWork with architecture teams and put up the micro-architecture based on the IP requirements\nDevelop RTL using Verilog/SystemVerilog/VHDL based on micro-architectural specifications\nTranslate system-level requirements into high-quality IP designs\nOptimize designs for power, performance, and area\nPerform design checks such as Lint, CDC, synthesis, and STA\nDrive bug fixing and closure\nSupport design reviews and sign-off processes\nCollaborate with verification teams on test plans and coverage closure\nRequired skills\nStrong experience in RTL design (Verilog/SystemVerilog/VHDL)\nSolid understanding of SoC/IP design and integration\nHands-on experience with:Lint, CDC, synthesis, timing analysis\nExperience in Low-power design techniques\nPreferred skills\nExperience in full-cycle IP/SoC development\nExposure to formal verification or low-power flows\nExperience with post-silicon validation and bring-up\n More information about NXP in India...\n#LI-29f4","description_format":"text","description_chars":1270,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-10-20T05:18:27Z"}],"visa":[],"liveness":{"score":53,"band":"ok","label":"Likely open","p_open":1,"p_active":0.585,"p_room":0.9,"age_days":24,"expected_fill_days":42,"reasons":["conf:26","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/nxp-semiconductors-senior-ip-design-engineer","json_url":"https://alion.io/job/nxp-semiconductors-senior-ip-design-engineer.json","meta":{"generated_at":"2026-10-23T21:37:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3853,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":17368},"rest":"https://alion.io/mcp/rest/get_company?id=17368"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fnxp-semiconductors-senior-ip-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fnxp-semiconductors-senior-ip-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fnxp-semiconductors-senior-ip-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/nxp-semiconductors-senior-ip-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fnxp-semiconductors-senior-ip-design-engineer"}]}