{"id":1228872,"url":"https://alion.io/job/nxp-semiconductors-sr-design-engineer","title":"Sr Design Engineer","company":{"id":17368,"name":"NXP Semiconductors","domain":"nxp.com","url":"https://alion.io/company/nxp","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":126,"ghost_share":0,"stale_share":0.802,"repost_share":0,"time_to_fill_p50_days":40,"computed_at":"2026-09-27T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Synopsys FineSim","optional":false},{"name":"Synopsys HSPICE","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-25T14:18:21Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-09-27T22:10:31Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"Key Responsibilities\nDesign and develop custom IO circuits including:GPIO\nLVDS\nLVCMOS\nSSTL\nHSTL\nDDR Interfaces\nHigh-speed SerDes support circuits\n\nPerform transistor-level design and simulation using advanced CMOS technology nodes.\nDevelop and optimize:ESD protection circuits\nLevel shifters\nInput buffers\nOutput drivers\nOn-chip termination circuits\n\nConduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.\nPerform signal integrity analysis including:IBIS model generation\nPackage-aware simulations\nCrosstalk and reflection analysis\n\nDrive layout reviews and work closely with physical design teams to ensure design quality and performance targets.\nSupport silicon bring-up, characterization, debugging, and production ramp activities.\nCollaborate with system, package, reliability, and product engineering teams.\nDevelop and maintain design documentation, specifications, and verification reports.\nRequired Qualifications\nBachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.\n2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.\nStrong understanding of:CMOS device physics\nAnalog circuit design fundamentals\nIO architectures and standards\nESD design methodologies\n\nHands-on experience in custom circuit design using Cadence Virtuoso.\nExpertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.\nExperience with advanced technology nodes (16nm/7nm/5nm preferred).\nGood knowledge of LVS, DRC, EMIR, and reliability checks.\nFamiliarity with process corners, Monte Carlo analysis, and yield optimization techniques.\nPreferred Skills\nExperience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.\nKnowledge of package modeling and SI/PI analysis tools.\nUnderstanding of ESD standards such as HBM, CDM, and IEC.\nExperience in silicon validation and lab characterization.\nScripting skills in Python, Perl, Tcl, or SKILL.\nFamiliarity with IBIS and IBIS-AMI model generation.\nDesired Competencies\nStrong analytical and debugging skills.\nExcellent communication and cross-functional collaboration.\nAbility to lead technical discussions and mentor junior engineers.\nProven track record of delivering silicon successfully from specification to production.\nSelf-driven with strong problem-solving abilities.\nNice to Have\nExperience in automotive, AI/ML, networking, mobile, or data center SoCs.\nExposure to functional safety and reliability requirements.\nPrior ownership of complete IO IP development cycle.\nThis role is ideal for an engineer who has hands-on experience in IO circuit design, ESD, signal integrity, and silicon validation, and is looking to contribute to next-generation semiconductor products.\n More information about NXP in India...\n#LI-7013","description_format":"text","description_chars":2801,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","RF & Wireless Hardware","Analog & Power Semiconductors"],"lifecycle":[{"event":"open","at":"2026-09-25T14:18:21Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":40,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-09-27T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/nxp-semiconductors-sr-design-engineer","json_url":"https://alion.io/job/nxp-semiconductors-sr-design-engineer.json","meta":{"generated_at":"2026-09-28T02:59:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":1843,"day_limit":5000,"remaining_today":3157,"minute_limit":60,"resets_at":"2026-09-29T00:00:00Z"}}}