{"id":713012,"url":"https://alion.io/job/olix-ams-engineer","title":"AMS Engineer","company":{"id":678679,"name":"OLIX","domain":"olix.com","url":"https://alion.io/company/olix","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"A","score":95,"open_postings":14,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":89,"computed_at":"2026-11-07T05:47:08Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":264000,"max":264000,"currency":"USD","period":"year","gross":null,"usd_annual":264000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Python","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-06-19T09:19:59Z","employer_posted_date":"2026-06-19","last_verified_at":"2026-11-07T16:44:47Z","board_verified":true,"closed_at":null,"days_open":141,"trust":{"level":"ok","repost_count":0,"flags":[],"days_open":140},"description":"About OLIX\nAI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.\nThe Role\nWe are designing silicon for a new and innovative breakthrough AI computing solution using optics and high-speed interconnect. Verifying the mixed-signal subsystems of this solution is one of the hardest and highest-leverage problems in the design flow and it is where this role sits. As a Senior Mixed-Signal Verification Engineer, you will own the verification of analog and mixed-signal blocks across our high-speed IO RX/TX chains - CDRs, phase interpolators and clock generation, DFE/CTLE equalization, samplers and slicers, deserializers, and the digital control loops that wrap around them. You will work at the boundary where analog behavior meets digital control, building the models, environments, and methodology that let us find bugs in silicon-accurate simulation rather than in the lab.\nResponsibilities\nOwn the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.\n\nDefine the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.\n\nDevelop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.\n\nBuild self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.\n\nDrive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.\n\nDefine functional coverage and assertions that target analog corner behavior - saturation, overflow, polarity, loop stability, settling - not just digital state.\n\nDebug and root-cause failures across the analog/digital boundary, including discrepancies between behavioral and transistor-level results, and drive them to closure.\n\nPartner with analog and DSP designers to review specs, pin down interface contracts, and translate analog intent into checkable models, assertions, and tests.\n\nOwn block- and subsystem-level verification sign-off for tape-out, including coverage closure and a clear statement of what AMS did and did not verify (functional vs. performance).\n\nBuild and maintain regression infrastructure and flow automation, and improve AMS simulation throughput.\n\nContribute to silicon bring-up and lab correlation, feeding measured behavior back into model validation.\n\nSkills & Experience\nBS/MS in Electrical Engineering or related field, with 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP.\n\nHands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator).\n\nProficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components.\n\nDemonstrated ability to model analog blocks at the appropriate level of abstraction and to validate those models against transistor-level references.\n\nStrong debug skills across the analog/digital boundary, with a structured approach to test planning, functional coverage, and closure.\n\nComfort reading analog schematics and specifications and collaborating directly with analog and DSP designers.\n\nNice to have\nStrong working knowledge of high-speed SerDes / wireline architectures - CDR and clock recovery, equalization (CTLE, DFE), PLLs and clocking, samplers/slicers, and serialization/deserialization.\n\nExperience verifying calibration and adaptation loops (offset and I/Q calibration, DFE tap adaptation) and clock-domain-crossing logic between recovered and core clock domains.\n\nUVM or other constrained-random, metric-driven verification experience for the digital control wrapped around analog blocks.\n\nScripting for regression and flow automation (Python, TCL, Make).\n\nTrack record of mixed-signal IP sign-off through tape-out, plus silicon bring-up and measurement correlation.\n\nA clear understanding of where AMS verification ends and transistor-level performance sign-off begins.\n\nCompensation & Equity\nCompetitive Salary: Commensurate with your experience, skills, and location\n\nEquity & Ownership: Meaningful stock options. You’re not just joining the mission; you’re owning a piece of it\n\nProximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office\n\nRetirement Benefits: Employer-contributed retirement plans to help you build long-term financial security\n\nDue to U.S. export control regulations, candidates’ eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.","description_format":"text","description_chars":6120,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity","Retirement plans","Stock options"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-09-11T05:14:25Z"}],"visa":[{"country":"US","licensed_sponsor":true,"adverts_offering_sponsorship_24m":0,"sanctioned_now":false,"evidence":"green card filings: 1","filings_12m":0,"filings_prev_12m":1,"green_card_filings_12m":1,"median_offered_wage_usd":107500,"route":null,"cap_exempt":false,"checked_at":"2026-11-07T07:57:00+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0}],"liveness":{"score":29,"band":"fade","label":"Fading","p_open":1,"p_active":0.81,"p_room":0.36,"age_days":140,"expected_fill_days":89,"reasons":["conf:1","velocity","win:tail","crowd:"],"computed_at":"2026-11-07T05:47:08Z"},"pay":{"stated_usd_annual":264000,"is_top_pay":true},"html_url":"https://alion.io/job/olix-ams-engineer","json_url":"https://alion.io/job/olix-ams-engineer.json","meta":{"generated_at":"2026-11-07T18:49:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":28793,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-08T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":678679},"rest":"https://alion.io/mcp/rest/get_company?id=678679"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Folix-ams-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Folix-ams-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Folix-ams-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/olix-ams-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Folix-ams-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":713012}},{"tool":"search_jobs","arguments":{"company":"olix.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":713012},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}