{"id":122391,"url":"https://alion.io/job/omni-design-technologies-senior-dft-engineer","title":"Senior DFT Engineer","company":{"id":8204,"name":"Omni Design Technologies","domain":"omnidesigntech.com","url":"https://alion.io/company/omni-design-technologies","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"D","score":40,"open_postings":46,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":45000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Genus","optional":false},{"name":"Python","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2021-03-31T14:07:53Z","employer_posted_date":"2021-03-31","last_verified_at":"2026-10-21T19:17:52Z","board_verified":true,"closed_at":null,"days_open":2030,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":2029},"description":"We are looking for an experienced DFT engineer, who is capable of driving the required DFT flows for our digital designs. The ability to work closely with rtl and pnr design team to drive testability is a key feature of this role!\nQualifications\nHands-on expertise with commercial test generation tools for large complex designs\nStrong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST and LBIST\nExperience generating test patterns and analyzing and debugging test failures\nExperience with RTL simulation, synthesis and back end implementation flows\nExperience defining and implementing stuck-at and at-speed techniques\nExperience running test compression flow\nExperience trading off test options with product performance and schedule requirements\nExperience creating and releasing full test programs for device screening\nTest optimization\nResolve design and flow issues related to DFT, identify potential solutions, and drive execution\nEducation and Experience\nB.E./B.Tech./M.E./M.Tech in VLSI\nMinimum of 5 years of working experience in DFT flow of a product company.\nStrong fundamentals in digital ASIC design, experience with ASIC test, DFT, and debug\nDetailed Responsibilities and Skills\nDefine DFT strategy and methodologies\nDefine test structures, debug structures, test plans\nCreate test vectors, simulate in various modes\nCollaborate with physical design team to close requirements\nValidate DFT requirements are being met\nWork with designers to increase test coverage, debug observability and flexibility\nVerify post-PD designs meet DFT requirements\nKnowledge of full DFT flow (test structure insertion, pattern generation, simulation )\nHands-on experience with Cadence Genus, Modus tools,\nShould have good understanding of Verilog/VHDL\nExposure to low power techniques\nKnowledge of TCL and Python scripting is a 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