{"id":122383,"url":"https://alion.io/job/omni-design-technologies-verification-engineering-leadmanager","title":"Verification Engineering Lead/Manager","company":{"id":8204,"name":"Omni Design Technologies","domain":"omnidesigntech.com","url":"https://alion.io/company/omni-design-technologies","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"D","score":40,"open_postings":45,"ghost_share":1,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Milpitas, United States","Bengaluru, India"],"countries":["US","IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":151000,"max_usd":287000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":576},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Linux","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2025-01-21T22:30:53Z","employer_posted_date":"2025-01-21","last_verified_at":"2026-10-17T19:32:03Z","board_verified":true,"closed_at":null,"days_open":633,"trust":{"level":"ghost","repost_count":0,"flags":["stale","company_stale"],"days_open":633},"description":"The position involves designing, developing and deploying UVM based Testbenches for multi-core, multi-threaded processor subsystems with emphasis on verifying and signing off performance and power along with functionality for mixed signal SOC. The candidate should have worked on architecture of chip-level testbenches and verification of SoCs and chipsets with ARM/RISC-V processor technology and AMBA AHB/AXI/APB along with high-speed interfaces like PCIe, MIPI, USB, Ethernet, Mobile DDR and Quad/Octa-SPI and peripheral interfaces like SDIO, UART, I2S, I2C, PWM, QEI, CAN, Ethernet, PCIe, UCIe as well as Mixed Signal AMS simulation environment.\nRole and Responsibility\nLead the SOC and Mixed signal verification team and efforts\nBuild capable verification team and manage the tasks and the team to get to tape out on agreed upon schedule and to Production with Agreed upon turns. Revision 0 Silicon success is highly desired.\nDevelop and signoff on test plans and test cases\nStrong knowledge of digital design and two or three of AMBA AHB/AXI/APB based SoC Architecture, ADC/DAC, PCIe, Ethernet, CAN, LPDDR interfaces.\nstrong knowledge of Verilog, System Verilog, UVM, C/C++\nExperience in usage of assertions, constrained random generation, functional/code coverage\nKnowledge of scripting languages like Perl, Python, TCL, Linux shells to achieve automation of verification methodologies and flows\nAnalytical debugging skills\nExcellent team building and management skills\nQualifications and Experience\nBS in EE with 8+ years of experience or MS in EE with 6+ year experience\nKnowledge of at least one of high-speed interfaces like USB, MIPI, PCIe, Ethernet, DP,\nKnowledge of two or three of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, SPI\nExperience managing a verification team\nStrong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti\nFluent in verification languages such as UVM/OVM/System Verilog, Vera, Verilog\nExperience in writing Test-plans and creating directed and random test cases\nStrong scripting skills in Perl, Python, Linux shells etc.\nStrong problem-solving skill to quickly identify and provide solution under tight schedule pressure\nStrong analytical problem solving and attention to details\nTeam player with interest in filing up gaps in product development as needed\nGood written and verbal communication skills\nGood technical documentation skills\nGood interpersonal skills, self-motivated, self-starter\nExpectations\nDevelop the Test benchses for AMS and FC simulations\nBe UPF Aware.\nDevelop the tests to get 95+% coverage for the simulations\nWork with Design team to debug any failures\nIntegrate and run the BIST and DFT gate level sims.\nDo code, line and toggle coverage and other metrics.\nRun daily and weekly regressions and publish results\nResponsible for FC RTL, Gate level simulations\nBe a mentor and lead a team of Verification engineers\nWork with Systems and Test engineering team to help validate the parts and release them to production","description_format":"text","description_chars":3031,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Analog & Power Semiconductors","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2025-01-21T22:30:53Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 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